EUVD-2025-209812Severity by source
CVSS:4.0/AV:L/AC:H/AT:N/PR:H/UI:N/VC:H/VI:H/VA:N/SC:H/SI:H/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
Local host access with high privilege and specialized low-level knowledge (AV:L/AC:H/PR:H); escaping the host to compromise ASP/SEV-SNP guests changes scope (S:C) with high C/I but no availability impact.
Primary rating from NVD.
CVSS VectorNVD
Lifecycle Timeline
3DescriptionCVE.org
Missing lock bit protection for NBIO registers could allow a local admin-privileged attacker to gain arbitrary System Management Network (SMN) access, potentially resulting in arbitrary code execution in AMD Secure Processor (ASP) and loss of the SEV-SNP guest's confidentiality and integrity.
AnalysisAI
Privilege escalation into the AMD Secure Processor affects AMD EPYC 8004/9004/9005 and EPYC Embedded 8004/9004/9005 series processors, where missing lock bit protection on NBIO registers lets a local admin-privileged attacker gain arbitrary System Management Network (SMN) access. This can lead to arbitrary code execution inside the AMD Secure Processor (ASP) and breaks the confidentiality and integrity guarantees SEV-SNP is supposed to provide to confidential-computing guests. There is no public exploit identified at time of analysis, EPSS risk is negligible (0.01%), and CISA SSVC rates exploitation as none but technical impact as total.
Technical ContextAI
The affected component is the northbridge I/O (NBIO) hardware block on AMD EPYC (Zen 4 'Genoa'/'Bergamo' and Zen 5 'Turin') server SoCs, which exposes configuration registers reachable over the on-die System Management Network (SMN) - an internal fabric that routes to privileged microcontrollers including the AMD Secure Processor (ASP, formerly PSP). The root cause maps to CWE-1233 (Security-Sensitive Hardware Controls with Missing Lock Bit Protection): certain NBIO registers that should be latched read-only early in boot are left unlocked, so software that can still program them can redirect or open SMN access paths. Because the ASP is the hardware root of trust that enforces SEV-SNP memory encryption and attestation, gaining SMN reach into it collapses the isolation boundary between a compromised host and encrypted confidential-computing guests.
RemediationAI
Apply the AMD-provided firmware/AGESA-PI update for your specific processor family as delivered through your server OEM/BIOS vendor: EPYC 9004 and 8004 update to GenoaPI_1.0.0.H, EPYC 9005 to TurinPI_1.0.0.8, EPYC Embedded 8004/9004 (Genoa and Bergamo) to EmbGenoaPI-SP5 1.0.0.D, and EPYC Embedded 9005 to EmbeddedTurinPI_SP5_1004, all documented in AMD security bulletin AMD-SB-3030 (https://www.amd.com/en/resources/product-security/bulletin/AMD-SB-3030.html). Because the fix is microcode/PI-level, it must be deployed via a BIOS/UEFI update from the platform vendor and typically requires a reboot to take effect. Where patching must be deferred, the practical compensating control is to tightly restrict who holds host root/administrator on SEV-SNP hosts and to treat unpatched hosts as outside the confidential-computing trust boundary - that is, do not run sensitive SEV-SNP guests on them and enforce remote attestation that rejects the vulnerable firmware version; the trade-off is reduced capacity/flexibility for confidential workloads until firmware is updated.
Local privilege escalation in the AMD Platform Configuration Blob (APCB) SMM driver, shipped in AGESA firmware across ne
Missing hardware lock bit protection on NBIO registers in AMD EPYC server processors (7003/8004/9004/9005 series, includ
Missing lock check in the AMD Platform Security Processor (PSP) across multiple EPYC server CPU generations enables a lo
Insuffient checks of the RMP on host buffer access in IOMMU may allow an attacker with privileges and a compromised HV t
Improper access control in the IOMMU register interface on AMD EPYC server processors allows a high-privileged local att
Share
External POC / Exploit Code
Leaving vuln.today