EUVD-2026-62483
GHSA-mfp2-3c3g-v44h
Severity by source
AV:N/AC:L/PR:N/UI:R/S:U/C:H/I:H/A:H
Local access and low privileges (user/supervisor code execution) required to trigger MRET; scope changes to machine-mode across privilege boundary; no user interaction needed.
Primary rating from Vendor (mitre).
CVSS VectorVendor: mitre
Lifecycle Timeline
4DescriptionCVE.org
An issue in Berkeley Out-of-Order Machine (BOOM) / BoomTile RTL benchmark v1.2 2d08d0d8b4563212175212f9db0e69f6e68c9619 allows a remote attacker to execute arbitrary code via the CSR trap-return state restoration logic, MRET handling logic, mstatus.MPRV update path, CSRFile logic in ProcessorFuzz BOOM benchmark Benchmarks/Verilog/SmallBoomTile_v1.2_state.v
AnalysisAI
Privilege escalation and arbitrary code execution affect the Berkeley Out-of-Order Machine (BOOM) RISC-V processor RTL implementation at commit 2d08d0d8b4563212175212f9db0e69f6e68c9619 (v1.2), specifically within the machine-mode trap-return (MRET) and mstatus.MPRV state-restoration logic in the CSRFile. An attacker who can execute unprivileged or supervisor-mode code on a system running the BOOM core can potentially abuse the flawed privilege-restoration path to gain machine-mode (M-mode) access, achieving full system control. …
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Attack ChainAIDerived
Hypothetical attack flow derived from CVE metadata
Vulnerability AssessmentAI
| Exploitation | Exploitation requires the ability to execute arbitrary RISC-V instructions on a processor core implemented using the BOOM RTL at the specific affected commit (v1.2, 2d08d0d8b4563212175212f9db0e69f6e68c9619), whether via simulation (e.g., Verilator, VCS) or FPGA synthesis. … Additional conditions and limiting factors are described in the full assessment. |
| Risk Assessment | The CVSS 3.1 base score of 8.8 with vector AV:N/AC:L/PR:N/UI:R/S:U/C:H/I:H/A:H is internally inconsistent with the described vulnerability. … Full risk analysis with EPSS, KEV, and SSVC signal comparison available after sign-in. |
| Exploit Scenario | Full exploit scenario with step-by-step reproduction available after sign-in. |
| Remediation | No vendor-released patch or tagged fix version has been identified in the available data; the upstream fix status should be confirmed directly via the riscv-boom GitHub repository at https://github.com/riscv-boom/riscv-boom. … Detailed patch versions, workarounds, and compensating controls in full report. |
Recommended ActionAI
Immediately inventory all systems running BOOM RISC-V processor core v1.2 (commit 2d08d0d8b4563212175212f9db0e69f6e68c9619) and restrict network and physical access to limit exposure to untrusted code execution. …
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External POC / Exploit Code
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