EUVD-2026-23954
GHSA-9m35-v5wh-m3xw
Severity by source
AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H
Primary rating from NVD · only source for this CVE.
CVSS VectorNVD
Lifecycle Timeline
5DescriptionCVE.org
A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as "writes preserve values, reads ignore values," i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.
AnalysisAI
Privileged CSR manipulation in XiangShan RISC-V processor core (commit aecf601e80, 2024-11-19) allows local attackers with M-mode access to corrupt processor status registers by exploiting improper handling of WPRI (Write Preserve, Read Ignore) fields in menvcfg operations. Carefully crafted csrrs instructions targeting menvcfg unexpectedly set reserved bits in xstatus to 1, violating RISC-V specification requirements that WPRI fields remain unchanged during CSR operations. Upstream fix committed (5e3dd63) but released version not confirmed. EPSS score 5th percentile indicates low real-world exploitation probability despite theoretical high impact, with no active exploitation or public POC identified.
Technical ContextAI
XiangShan is an open-source out-of-order RISC-V processor core developed by the Institute of Computing Technology, Chinese Academy of Sciences. This vulnerability affects the Control and Status Register (CSR) subsystem, specifically the Machine Environment Configuration register (menvcfg) implementation. RISC-V privileged specification defines WPRI (Write Preserve, Read Ignore) fields as reserved bit ranges that must maintain their values across CSR operations - software modifying other fields should not alter WPRI bits, and reads should return predictable values. The menvcfg register, introduced in RISC-V privileged spec version 1.12 for configuring machine-mode environment features, contains multiple WPRI fields. The vulnerability maps to CWE-1244 (Internal Asset Exposed to Unsafe Debug Access Level), indicating improper isolation between debug/privileged operations and architectural state. The affected commit (aecf601e803bfd2371667a3fb60bfcd83c333027) from November 2024 suggests the flaw was introduced during recent menvcfg implementation or refactoring work in the XiangShan core's CSR handling logic.
RemediationAI
Update XiangShan processor core to commit 5e3dd63 or later from the upstream repository (https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63), which addresses the menvcfg WPRI field handling flaw. Hardware vendors integrating XiangShan must resynththesize RTL, reverify the design, and redistribute updated FPGA bitstreams or tape out corrected silicon - note that silicon fixes require full chip respins with 6-12 month lead times and may not be economically feasible for low-volume products. For deployed systems running vulnerable XiangShan cores where hardware updates are impractical, implement firmware-level mitigations: minimize or eliminate dynamic menvcfg modifications in M-mode code (bootloaders, secure monitors, hypervisors), validate xstatus register contents after any menvcfg operations with explicit bit-masking to clear reserved fields, and restrict M-mode code execution to vendor-signed firmware only via secure boot mechanisms. These compensating controls reduce attack surface but cannot eliminate the hardware-level flaw. RISC-V specification references for validation: machine-mode CSR documentation at https://docs.riscv.org/reference/isa/priv/machine.html and WPRI field semantics at https://docs.riscv.org/reference/isa/priv/priv-csrs.html. Note that firmware workarounds add runtime overhead to CSR operations and may impact real-time performance in embedded applications.
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