EUVD-2025-210801
GHSA-f8v4-7pm5-xqfx
Attack ChainAIDerived
Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain
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AccessGain code execution on OR1200 core
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ExploitIssue crafted instruction sequence
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ExecutionTrigger RTL/netlist divergence in hardware
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ImpactLeak internal state or fault core
Vulnerability Assessment
| Weakness |
CWE
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| Exploitation Conditions | Exploitation requires that the target hardware was synthesized from the affected OR1200 core at commit 83ac6b such that the RTL-to-netlist mismatch is actually present in the fabricated device or FPGA image, and that the attacker can execute a specific triggering instruction sequence on that core. Limiting factors: the flaw manifests only in the synthesized netlist (RTL-only simulation would not exhibit it), it is tied to a specific commit and synthesis flow, the affected core is a niche open-source soft-core, and there is no evidence the published AV:N (network) vector is real - realistic access is local execution on or design-time control of the core, not remote unauthenticated reach. |
| Impact | The signals conflict sharply. The published CVSS 3.1 vector (AV:N/AC:L/PR:N/UI:N/C:H/A:H, base 9.1) implies trivial remote unauthenticated compromise, but that is implausible for a CPU soft-core: a network attack vector for an RTL/netlist mismatch is unsupported by the description and almost certainly a mis-scored vector - realistic exploitation is local code execution on, or physical/design-time access to, the synthesized core. EPSS is very low (0.15%, percentile 5) and the CVE is not in CISA KEV, so there is no evidence of active exploitation; no POC is provided beyond academic detection tooling. Tags label it 'Information Disclosure,' which is inconsistent with the input vector's C:H/A:H (which claims availability impact but no integrity impact). Bottom line: this is a high-nominal-CVSS but low-real-world-priority research-grade finding for most defenders - verify the actual attack vector with the OpenRISC maintainers before treating the 9.1 as accurate. |
| Exploit ScenarioDerived | An attacker able to execute code on a device built from the affected OR1200 netlist crafts an instruction sequence that hits the region where synthesized hardware diverges from the verified RTL, causing the core to leak internal state or enter an unexpected fault/hang. Because exploitation depends on the physical/synthesized silicon or FPGA image rather than a network service, the realistic actor is one with local execution or supply-chain/design access; no public exploit code is available, only academic detection tooling. |
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Alert meAnalysisAIv1 – Aug 27, 2026
Information disclosure in the OpenRISC OR1200 processor soft-core (commit 83ac6b) arises from a mismatch between the RTL source and the synthesized netlist, meaning the fabricated/synthesized hardware behaves differently than the verified design and can leak confidential state or misbehave. The flaw was surfaced by the academic SynFuzz RTL-vs-netlist fuzzing research (arXiv:2504.18812) rather than by field exploitation; no public exploit identified at time of analysis and EPSS is low (0.15%, 5th percentile). The NVD CVSS of 9.1 (C:H/A:H) is far more alarming than the vague one-line description supports, so the score should be treated skeptically.
RemediationAI
No vendor-released patch version is identified at time of analysis - OR1200 is a community RTL project rather than a versioned vendor product, so the primary action is to pull the latest OpenRISC OR1200/mor1kx source past commit 83ac6b and re-run logical-equivalence checking between your RTL and synthesized netlist before taping out or programming FPGAs. Track the upstream issue at https://github.com/openrisc/mor1kx/issues/161 and review the SynFuzz materials (https://www.arxiv.org/abs/2504.18812, https://mason.gmu.edu/~rsaravan/projects/synfuzz/cve/cve.html) to reproduce the detection. As compensating controls for designs already fielded: add formal RTL-vs-netlist equivalence checking to your synthesis flow (trade-off: added EDA tooling cost and runtime), constrain synthesis optimization directives that may have introduced the divergence (trade-off: possible area/timing regression), and restrict who can load bitstreams/run untrusted code on the core (trade-off: operational friction). These are integration-time mitigations; there is no runtime signature to block.
Affected VersionsENISA
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Technical ContextAI · show details
OR1200 is a 32-bit RISC CPU implementation of the open OpenRISC 1000 architecture, distributed as synthesizable RTL (Verilog) intended for FPGA/ASIC integration. The root cause is classified as CWE-1281 (sequence of processor instructions / hardware logic leading to unexpected behavior); concretely the defect is an RTL-to-netlist equivalence failure, where logic optimization or synthesis produces a gate-level netlist that is not functionally equivalent to the register-transfer design that was verified. Such mismatches are exactly what the referenced SynFuzz project (mason.gmu.edu synfuzz, arXiv 2504.18812) is built to detect by fuzzing and cross-checking RTL simulation against the post-synthesis netlist. Note the CPE is a placeholder ('cpe:2.3:a:n/a:n/a:*') and one reference actually points to the mor1kx core issue tracker rather than OR1200, so exact affected-component boundaries are not cleanly established in the source data.
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Severity by source
AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H
A synthesized-hardware mismatch is not network-reachable, so AV:L; triggering the specific divergence with code execution on the core gives AC:H/PR:L, with confidentiality and availability impact but no integrity change.
Primary rating from Vendor (mitre).
CVSS VectorVendor: mitre
Lifecycle Timeline
3DescriptionCVE.org
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.
Executive ViewAI
OpenRISC OR1200 processor soft-core contains an information disclosure vulnerability stemming from a mismatch between verified design and synthesized hardware implementation, potentially allowing confidential data leakage or system misbehavior in affected silicon. Organizations must immediately determine whether this open-source processor core is incorporated into any products or systems, as the CVSS 9.1 rating indicates high-impact confidentiality and availability risks if deployed.
No vendor-released patch identified at time of analysis. Interim mitigations include: transitioning to alternative, formally verified processor cores; implementing independent RTL-versus-netlist verification for any OR1200 modifications prior to synthesis; engaging third-party hardware security auditors to validate design-implementation correspondence before silicon fabrication; restricting affected processor versions to non-sensitive applications until remediation is available.
Threat Intelligence Overview
NVD
CVE.org
EPSS
How this decision was reached
The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.
What every action level means
SSVC AssessmentENISA
Priority Score
Attack Technique
Information disclosure occurs when an application unintentionally exposes sensitive data that aids attackers in reconnaissance or directly compromises security.
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