EUVD-2025-210801
GHSA-f8v4-7pm5-xqfx
Severity by source
AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H
A synthesized-hardware mismatch is not network-reachable, so AV:L; triggering the specific divergence with code execution on the core gives AC:H/PR:L, with confidentiality and availability impact but no integrity change.
Primary rating from Vendor (mitre).
CVSS VectorVendor: mitre
Lifecycle Timeline
4DescriptionCVE.org
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.
AnalysisAI
Information disclosure in the OpenRISC OR1200 processor soft-core (commit 83ac6b) arises from a mismatch between the RTL source and the synthesized netlist, meaning the fabricated/synthesized hardware behaves differently than the verified design and can leak confidential state or misbehave. The flaw was surfaced by the academic SynFuzz RTL-vs-netlist fuzzing research (arXiv:2504.18812) rather than by field exploitation; no public exploit identified at time of analysis and EPSS is low (0.15%, 5th percentile). The NVD CVSS of 9.1 (C:H/A:H) is far more alarming than the vague one-line description supports, so the score should be treated skeptically.
Technical ContextAI
OR1200 is a 32-bit RISC CPU implementation of the open OpenRISC 1000 architecture, distributed as synthesizable RTL (Verilog) intended for FPGA/ASIC integration. The root cause is classified as CWE-1281 (sequence of processor instructions / hardware logic leading to unexpected behavior); concretely the defect is an RTL-to-netlist equivalence failure, where logic optimization or synthesis produces a gate-level netlist that is not functionally equivalent to the register-transfer design that was verified. Such mismatches are exactly what the referenced SynFuzz project (mason.gmu.edu synfuzz, arXiv 2504.18812) is built to detect by fuzzing and cross-checking RTL simulation against the post-synthesis netlist. Note the CPE is a placeholder ('cpe:2.3:a:n/a:n/a:*') and one reference actually points to the mor1kx core issue tracker rather than OR1200, so exact affected-component boundaries are not cleanly established in the source data.
RemediationAI
No vendor-released patch version is identified at time of analysis - OR1200 is a community RTL project rather than a versioned vendor product, so the primary action is to pull the latest OpenRISC OR1200/mor1kx source past commit 83ac6b and re-run logical-equivalence checking between your RTL and synthesized netlist before taping out or programming FPGAs. Track the upstream issue at https://github.com/openrisc/mor1kx/issues/161 and review the SynFuzz materials (https://www.arxiv.org/abs/2504.18812, https://mason.gmu.edu/~rsaravan/projects/synfuzz/cve/cve.html) to reproduce the detection. As compensating controls for designs already fielded: add formal RTL-vs-netlist equivalence checking to your synthesis flow (trade-off: added EDA tooling cost and runtime), constrain synthesis optimization directives that may have introduced the divergence (trade-off: possible area/timing regression), and restrict who can load bitstreams/run untrusted code on the core (trade-off: operational friction). These are integration-time mitigations; there is no runtime signature to block.
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External POC / Exploit Code
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