Monthly
Information disclosure in the OpenRISC OR1200 processor soft-core (commit 83ac6b) arises from a mismatch between the RTL source and the synthesized netlist, meaning the fabricated/synthesized hardware behaves differently than the verified design and can leak confidential state or misbehave. The flaw was surfaced by the academic SynFuzz RTL-vs-netlist fuzzing research (arXiv:2504.18812) rather than by field exploitation; no public exploit identified at time of analysis and EPSS is low (0.15%, 5th percentile). The NVD CVSS of 9.1 (C:H/A:H) is far more alarming than the vague one-line description supports, so the score should be treated skeptically.
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via. Rated high severity (CVSS 7.5), this vulnerability is remotely exploitable, no authentication required, low attack complexity. Public exploit code available and no vendor patch available.
Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated user to potentially enable escalation of privilege via local. Rated medium severity (CVSS 5.3). No vendor patch available.
Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some Intel(R) Xeon(R) Processors may allow an authenticated user to potentially enable denial of service. Rated medium severity (CVSS 4.8), this vulnerability is low attack complexity. No vendor patch available.
Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may allow an authenticated user to potentially enable escalation of privilege and/or information. Rated high severity (CVSS 7.8), this vulnerability is low attack complexity. No vendor patch available.
Information disclosure in the OpenRISC OR1200 processor soft-core (commit 83ac6b) arises from a mismatch between the RTL source and the synthesized netlist, meaning the fabricated/synthesized hardware behaves differently than the verified design and can leak confidential state or misbehave. The flaw was surfaced by the academic SynFuzz RTL-vs-netlist fuzzing research (arXiv:2504.18812) rather than by field exploitation; no public exploit identified at time of analysis and EPSS is low (0.15%, 5th percentile). The NVD CVSS of 9.1 (C:H/A:H) is far more alarming than the vague one-line description supports, so the score should be treated skeptically.
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via. Rated high severity (CVSS 7.5), this vulnerability is remotely exploitable, no authentication required, low attack complexity. Public exploit code available and no vendor patch available.
Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated user to potentially enable escalation of privilege via local. Rated medium severity (CVSS 5.3). No vendor patch available.
Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some Intel(R) Xeon(R) Processors may allow an authenticated user to potentially enable denial of service. Rated medium severity (CVSS 4.8), this vulnerability is low attack complexity. No vendor patch available.
Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may allow an authenticated user to potentially enable escalation of privilege and/or information. Rated high severity (CVSS 7.8), this vulnerability is low attack complexity. No vendor patch available.