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OR1200 CVE-2025-51677

CRITICAL
Improper Encoding or Escaping of Output (CWE-116)
2026-07-17 mitre
9.1
CVSS 3.1 · Vendor: mitre
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Severity by source

Vendor (mitre) PRIMARY
9.1 CRITICAL
AV:N/AC:L/PR:N/UI:N/S:U/C:N/I:H/A:H
vuln.today AI
3.0 LOW

Hardware synthesis/output-port mismatch reachable only on a specific locally deployed netlist build (AV:L, AC:H, PR:H); impact is uncertain misbehavior, so I:L/A:L and C:N.

3.1 AV:L/AC:H/PR:H/UI:N/S:U/C:N/I:L/A:L
4.0 AV:L/AC:H/AT:N/PR:H/UI:N/VC:N/VI:L/VA:L/SC:N/SI:N/SA:N

Primary rating from Vendor (mitre).

CVSS VectorVendor: mitre

Attack Vector
Network
Attack Complexity
Low
Privileges Required
None
User Interaction
None
Scope
Unchanged
Confidentiality
None
Integrity
High
Availability
High

Lifecycle Timeline

4
Analysis Generated
Jul 20, 2026 - 19:25 vuln.today
CVSS changed
Jul 20, 2026 - 19:22 NVD
9.1 (CRITICAL)
CVE Published
Jul 17, 2026 - 00:00 cve.org
CRITICAL 9.1
CVE Published
Jul 17, 2026 - 00:00 cve.org
UNKNOWN (no severity yet)

DescriptionCVE.org

An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior.

AnalysisAI

Output-handling discrepancy in the OpenRISC OR1200 soft-core CPU (commit 83ac6b) causes the CPU output port to differ between the RTL source and the synthesized netlist, producing unexpected hardware behavior. The flaw was surfaced by the academic SynFuzz hardware-fuzzing research (arXiv 2504.18812) rather than in-the-wild attacks, affects the open-source mor1kx/OR1200 core used mainly in research and FPGA/SoC prototyping, and has no public exploit identified at time of analysis. Assigned CVSS 9.1 (NVD/MITRE) but with a very low EPSS of 0.17% (6th percentile), reflecting a research-grade correctness finding rather than a mass-exploitation threat.

Technical ContextAI

OR1200 is a 32-bit Harvard-architecture RISC soft-core implementing the OpenRISC 1000 ISA, typically synthesized to FPGA or ASIC and integrated as a CPU core in SoC designs; mor1kx is its successor implementation where the issue was tracked (GitHub issue #160). The reported problem is an equivalence gap between the register-transfer-level (RTL) description and the post-synthesis gate-level netlist on a CPU output port - i.e., logic synthesis produces hardware whose observable output does not match the simulated RTL semantics. CWE-116 (Improper Encoding or Escaping of Output) is used here loosely to label an output-representation mismatch; the true root cause is an RTL-vs-netlist functional equivalence failure detected by differential hardware fuzzing (SynFuzz), a class of defect normally caught by formal equivalence checking rather than a classic software output-encoding bug.

RemediationAI

No vendor-released patch version is identified at time of analysis; the OpenRISC/mor1kx projects are community-maintained and the finding is documented in GitHub issue #160 (https://github.com/openrisc/mor1kx/issues/160#issuecomment-2585618940) and the SynFuzz research (https://www.arxiv.org/abs/2504.18812, https://mason.gmu.edu/~rsaravan/projects/synfuzz/cve/cve.html). Because this is a hardware synthesis correctness issue, the actionable controls are design-flow rather than runtime: run formal RTL-to-netlist logical equivalence checking (LEC) on your synthesized OR1200/mor1kx core to detect and reject the mismatched output-port logic before tapeout or bitstream deployment, pin to a reviewed commit rather than the affected 83ac6b, and add the SynFuzz-identified case to your regression/simulation vectors. If you cannot re-synthesize, avoid relying on the affected CPU output port for security-relevant decisions and validate its behavior against RTL simulation; the trade-off is added verification time and potential timing/area changes when the RTL is corrected.

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CVE-2025-51677 vulnerability details – vuln.today

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