Severity by source
AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H
Requires M-mode (highest-privilege) code execution inside the emulator so AV:L/PR:H; primary impact is DoS (A:H) with minor config-enforcement integrity (I:L) and no confidentiality loss.
Primary rating from NVD.
CVSS VectorNVD
Lifecycle Timeline
5DescriptionCVE.org
NEMU contains an implementation flaw in its RISC-V Hypervisor CSR handling where henvcfg[7:4] (CBIE/CBCFE/CBZE-related fields) is incorrectly masked/updated based on menvcfg[7:4], so a machine-mode write to menvcfg can implicitly modify the hypervisor's environment configuration. This can lead to incorrect enforcement of virtualization configuration and may cause unexpected traps or denial of service when executing cache-block management instructions in virtualized contexts (V=1).
AnalysisAI
Denial of service and incorrect virtualization-configuration enforcement affect NEMU, the OpenXiangShan RISC-V full-system emulator, because its Hypervisor CSR logic derives henvcfg[7:4] (the CBIE/CBCFE/CBZE cache-block-management fields) from menvcfg[7:4] via an erroneous mask on read. As a result, machine-mode code that writes menvcfg implicitly mutates the hypervisor environment configuration, so guest code running virtualized (V=1) can hit unexpected traps or a denial-of-service when executing cache-block-operation (cbo.*) instructions. No public exploit is identified at time of analysis; EPSS is 0.01% and CISA SSVC lists exploitation as 'none', which conflicts sharply with the 9.8 NVD base score.
Technical ContextAI
NEMU emulates the RISC-V privileged architecture, including the M-mode CSR menvcfg and the hypervisor-extension CSR henvcfg. Per the RISC-V privileged and hypervisor specs (referenced in the advisory), menvcfg controls the environment configuration seen at lower privilege, while henvcfg independently controls the environment configuration for a virtualized guest (V=1); the low nibble [7:4] governs cache-block instruction behavior (Zicbom/Zicboz - CBIE, CBCFE, CBZE). The emulator bug is a protection-mechanism failure (CWE-693): in csr_read the henvcfg value was being AND-masked with menvcfg->val & MENVCFG_WMASK, so henvcfg's cache-block fields were tied to menvcfg instead of being maintained separately. The PR #689 fix removes the line 'henvcfg_out &= menvcfg->val & MENVCFG_WMASK;', restoring independent hypervisor configuration semantics. This is a functional-correctness flaw in an emulator's modeling of RISC-V CSRs, not a memory-safety defect in a network service.
RemediationAI
Upstream fix available (PR/commit); released patched version not independently confirmed - apply the change in pull request https://github.com/OpenXiangShan/NEMU/pull/689, which removes the erroneous masking of henvcfg by menvcfg in src/isa/riscv64/system/priv.c (see issue https://github.com/OpenXiangShan/NEMU/issues/681). No tagged release version is provided in the input, so rebuild NEMU from a source tree that includes that commit rather than relying on a specific version tag. As NEMU is a development/verification tool, the practical compensating control until you rebuild is to avoid relying on NEMU's henvcfg cache-block (Zicbom/Zicboz) behavior for hypervisor-configuration correctness in test harnesses, and to treat any DoS/unexpected-trap results from virtualized (V=1) cbo.* instruction tests as suspect; there is no production service to firewall or feature-disable here, so no networking or access-control mitigation is applicable.
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Same weakness CWE-693 – Protection Mechanism Failure
View allSame technique Denial Of Service
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External POC / Exploit Code
Leaving vuln.today
EUVD-2026-23944