EUVD-2026-24131
GHSA-p2hj-qw82-grpc
Severity by source
AV:L/AC:L/PR:L/UI:N/S:U/C:L/I:L/A:L
Primary rating from NVD · only source for this CVE.
CVSS VectorNVD
Lifecycle Timeline
5DescriptionCVE.org
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses, affected XiangShan versions may still propagate such writes to replicated PMA configuration state. Local attackers able to execute code on the core (privilege context depends on system integration) can exploit this to tamper with memory-attribute enforcement, potentially leading to privilege escalation, information disclosure, or denial of service depending on how PMA enforces platform security and isolation boundaries.
AnalysisAI
XiangShan open-source RISC-V processor commit edb1dfaf7d290ae99724594507dc46c2c2125384 and earlier versions fail to properly gate the Control and Status Register (CSR) write-enable path for Physical Memory Attribute (PMA) configuration, allowing local attackers with code execution privileges to write to PMA CSRs that should raise illegal-instruction exceptions per the RISC-V specification. Successful exploitation enables attackers to alter memory attribute enforcement, potentially leading to privilege escalation, information disclosure, or denial of service depending on platform security boundaries. No public exploit code or active exploitation has been confirmed at time of analysis.
Technical ContextAI
XiangShan is an open-source high-performance RISC-V processor design. Control and Status Registers (CSRs) are privileged registers in RISC-V that control processor behavior; the RISC-V Privileged Architecture Specification mandates that illegal CSR accesses raise illegal-instruction exceptions. Physical Memory Attributes (PMA) are configuration CSRs that govern memory access permissions and enforcement. The vulnerability stems from improper gating logic in the distributed CSR write-enable path, a design-level control mechanism that should prevent writes to PMA registers that do not exist or are not accessible in the current privilege context. Instead of blocking these illegal writes and raising exceptions as required, the affected design allows writes to propagate to replicated PMA state, violating the RISC-V specification contract. The root cause is classified under CWE-284 (Improper Access Control), reflecting the failure to enforce register access restrictions at the hardware level.
RemediationAI
Apply the upstream fix from commit 2b1f9796aa98597e5eeac32e5bb1418496987ca4 (https://github.com/OpenXiangShan/XiangShan/commit/2b1f9796aa98597e5eeac32e5bb1418496987ca4), which corrects the CSR write-enable gating logic to properly enforce RISC-V specification requirements for illegal CSR accesses. Since XiangShan is open-source hardware design, remediation requires rebuilding and deploying the updated RTL (register-transfer language) design; organizations using synthesized XiangShan cores must regenerate masks or bitstreams from the patched source. For deployed silicon or embedded systems, hardware remediation may not be feasible; compensating controls include disabling or restricting PMA-dependent security features if they are optional, applying operating-system-level memory protection that does not rely on PMA (such as page-table-based isolation), and restricting local code execution privileges to trusted software only. Organizations integrating XiangShan should review whether PMA is used for critical security isolation; if so, prioritize design update and redeployment. Detailed PMA documentation is available at https://xiangshan-doc-test.readthedocs.io/next/memory/mmu/pmp_pma/.
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Same weakness CWE-284 – Improper Access Control
View allSame technique Authentication Bypass
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External POC / Exploit Code
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