Linux Kernel CVE-2026-72154

OpenRISC is an open-source RISC processor architecture with upstream Linux kernel support. The jump_label subsystem enables efficient static key patching by rewriting branch instructions in the kernel text segment at runtime, avoiding the overhead of a runtime conditional check. On SMP systems, after the kernel patches binary text on one core, all remote cores must explicitly invalidate their instruction caches (icaches) to ensure they fetch the updated instructions rather than stale cached copies. The original OpenRISC implementation (commit 8c30b0018f9d) was adapted from arm64 and used kick_all_cpus_sync(), which sends an inter-processor interrupt (IPI) whose callback is a no-op on remote cores. While executing the IPI handler does incidentally evict some cache lines, it does not guarantee a complete icache flush and is architecturally incorrect for OpenRISC. A secondary issue affects architectures without WRITETHROUGH data caches: without an explicit dcache flush after patching, the updated bytes may not be visible to the icache at all. No CWE was assigned by NVD; the root cause maps conceptually to improper cache coherency management in a multi-core context (related to CWE-1232).