Skip to main content

Linux Kernel CVE-2026-46148

| EUVDEUVD-2026-32775 MEDIUM
2026-05-28 416baaa9-dc9f-4396-8d5f-8c081fb06d67 GHSA-v9m3-f9j3-xrv6
5.5
CVSS 3.1 · NVD
View

Attack ChainAIDerived

Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain

  1. Access
    Identify target system with multi-device coreQSPI topology
  2. Delivery
    Gain local low-privilege access on affected kernel
  3. Exploit
    Initiate SPI transaction targeting GPIO-CS device
  4. Execution
    Hardware CS auto-asserts on unintended built-in-CS device
  5. Persist
    Bus contention or unexpected device activation
  6. Impact
    SPI peripheral/driver failure causes system availability impact

Vulnerability Assessment

Exploitation Conditions

Four simultaneous conditions are required: (1) the system runs a Linux kernel between commit 8596124c4c1bc7561454cee0463c16eca70b5d25 and the fix commits - specifically pre-6.18.30, pre-7.0.7, or pre-7.1-rc3; (2) a Microchip coreQSPI IP controller is present in the hardware and bound to the affected driver; (3) at least two SPI devices are wired to the same coreQSPI controller - one relying on the built-in hardware CS and one using a GPIO CS; and (4) a local process with SPI device access (PR:L) initiates a transaction to the GPIO-CS device. The flaw does NOT trigger on single-device QSPI configurations or on systems where all devices use exclusively GPIO chip selects - the latter was noted as common in boards with multiple devices, which is why this bug went undetected for an extended period. Physical hardware topology is the primary limiting factor; this cannot be exploited remotely or against general-purpose Linux servers.

Impact

The NVD CVSS 3.1 vector AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H (5.5 Medium) is broadly accurate: exploitation is local, requires low-privilege access, and produces only availability impact with no confidentiality or integrity consequences. EPSS at 0.02% (4th percentile) strongly corroborates that this is not a target of opportunistic exploitation - it is a driver correctness bug in a niche embedded SPI controller. The absence of a KEV listing and any public proof-of-concept code further reduces real-world urgency. Importantly, the EUVD 'Information Disclosure' tag is inconsistent with the CVSS C:N metric and the description's content; this tag appears to be a classification error and should not be treated as a signal of data exfiltration risk. The highest realistic risk is incidental rather than adversarial: a local process initiating SPI I/O on a system with the affected hardware topology could destabilize the SPI bus and cause peripheral or kernel driver failure. Priority should be low except for operators of Microchip PolarFire SoC systems with multi-device QSPI topologies running unpatched kernels.

Exploit ScenarioDerived

A local low-privilege user or process on an embedded Linux system (such as a Microchip PolarFire SoC board) running an unpatched kernel initiates an SPI transaction to a device connected via GPIO chip select. The coreQSPI hardware concurrently asserts the built-in CS line, placing an unintended active signal on a second SPI device sharing the same bus, causing that device's driver to receive corrupted or unexpected data - potentially triggering a kernel oops, SPI controller lockup, or peripheral reset that renders the system partially or fully unavailable. No public exploit code exists; the trigger is effectively any legitimate SPI transaction on the affected hardware.

This Month Plan within 30 days. Why: MEDIUM severity (CVSS 4.0-6.9).
Patch available 0.0% exploitation probability (EPSS)

Get an e-mail when this CVE is exploited, patched or re-scored. Free account.

Alert me

AnalysisAIv1 – Jun 10, 2026

Incorrect hardware chip-select management in the Linux kernel spi/microchip-core-qspi driver causes the built-in hardware CS line to assert spuriously during SPI transactions directed at GPIO-managed chip selects on multi-device coreQSPI controllers. Systems using Microchip coreQSPI IP hardware with two or more attached SPI devices - where at least one device uses the built-in hardware CS - are subject to unintended bus assertion that can crash or disrupt SPI-dependent peripherals, producing a high-availability impact. No public exploit exists and EPSS stands at 0.02% (4th percentile), consistent with the narrow embedded-hardware topology required for manifestation; the vulnerability is not in CISA KEV.

RemediationAI

The primary fix is to upgrade the Linux kernel to 6.18.30, 7.0.7, or 7.1-rc3 (or any later stable release), which contain the corrected spi/microchip-core-qspi driver. Fix commits are available at https://git.kernel.org/stable/c/7672749e1496215e8683ce57cf323119033954cf, https://git.kernel.org/stable/c/998f43196d732f20f9b71eb6ebd973736c9fa911, and https://git.kernel.org/stable/c/ee3c99aa102212ad59dc2c19595515c4a6729307 for downstream integration. If an immediate kernel upgrade is not feasible, a hardware-topology workaround is to ensure that all SPI devices attached to the coreQSPI controller exclusively use GPIO chip selects (not the built-in CS), which prevents the spurious CS assertion from affecting active devices; this may require board-level changes and is not available in all deployments. Note that the patch removes per-device CLKIDLE reconfiguration from the setup callback; operators relying on device-specific clock idle polarity may need to validate SPI device compatibility after upgrading to the patched kernel.

Affected VersionsENISA

Linux 8596124c4c1bc7561454cee0463c16eca70b5d25 <998f43196d732f20f9b71eb6ebd973736c9fa911
Linux 8596124c4c1bc7561454cee0463c16eca70b5d25 <ee3c99aa102212ad59dc2c19595515c4a6729307
Linux patch: 6.18.30
Linux 6.1
Linux patch: 7.1-rc3
Linux 8596124c4c1bc7561454cee0463c16eca70b5d25 <7672749e1496215e8683ce57cf323119033954cf
Linux patch: 0
Linux patch: 7.0.7

Affected Packages

euvd linux no fix

Source: OSV (Open Source Vulnerabilities)

Affects your stack

Affects 1 package in euvd

Checking this CVE against your own stacks and servers is part of the Basic plan and up.

Technical ContextAI · show details

The coreQSPI IP core is a Quad-SPI peripheral controller found on Microchip PolarFire SoC and related embedded platforms. Its built-in chip select was designed to be managed entirely by hardware: asserted when the transmit buffer is written and de-asserted once the byte count specified in the FRAMES.TOTALBYTES field has been transmitted. The driver historically did not place this CS under software control, relying on the hardware automaton. In multi-device topologies where additional SPI devices use GPIO lines as chip selects, the hardware CS automaton still fires during those unrelated GPIO-CS transactions, placing an unintended low signal on the built-in CS line. The fix transitions CS management to a software-controlled model using set_cs and exec_op callbacks, and removes the per-device setup reconfiguration of CLKIDLE/MASTER/ENABLE that was unsafe to run concurrently. No CWE is assigned; the root cause is a resource management logic error - failure to inhibit or gate the hardware CS path when it is not the intended target of a transaction. Affected product CPE: cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*.

Know when the next one hits your stack

  • Watch products and get an email when something new is published
  • Check this CVE against your own stack and servers
  • Exploit and PoC references, threat intelligence from 22 sources

No credit card · 7-day full trial

Severity by source

NVD PRIMARY 5.5 MEDIUM
AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:N/A:H
vuln.today AI 4.7 MEDIUM

AC:H over vendor AC:L because the specific multi-device coreQSPI hardware topology is a prerequisite entirely beyond attacker control; C and I remain N per description.

3.1 AV:L/AC:H/PR:L/UI:N/S:U/C:N/I:N/A:H
SUSE MEDIUM

Primary rating from NVD.

CVSS VectorNVD

Attack Vector
Local
Attack Complexity
Low
Privileges Required
Low
User Interaction
None
Scope
Unchanged
Confidentiality
None
Integrity
None
Availability
High

Lifecycle Timeline

4
CVSS changed
Jun 10, 2026 - 21:22 NVD
5.5 (MEDIUM)
Patch available
May 28, 2026 - 12:01 EUVD
CVE Published
May 28, 2026 - 10:16 nvd
MEDIUM 5.5
CVE Published
May 28, 2026 - 10:16 nvd
UNKNOWN (no severity yet)

DescriptionNVD

In the Linux kernel, the following vulnerability has been resolved:

spi: microchip-core-qspi: control built-in cs manually

The coreQSPI IP supports only a single chip select, which is automagically operated by the hardware - set low when the transmit buffer first gets written to and set high when the number of bytes written to the TOTALBYTES field of the FRAMES register have been sent on the bus. Additional devices must use GPIOs for their chip selects. It was reported to me that if there are two devices attached to this QSPI controller that the in-built chip select is set low while linux tries to access the device attached to the GPIO.

This went undetected as the boards that connected multiple devices to the SPI controller all exclusively used GPIOs for chip selects, not relying on the built-in chip select at all. It turns out that this was because the built-in chip select, when controlled automagically, is set low when active and high when inactive, thereby ruling out its use for active-high devices or devices that need to transmit with the chip select disabled.

Modify the driver so that it controls chip select directly, retaining the behaviour for mem_ops of setting the chip select active for the entire duration of the transfer in the exec_op callback. For regular transfers, implement the set_cs callback for the core to use.

As part of this, the existing setup callback, mchp_coreqspi_setup_op(), is removed. Modifying the CLKIDLE field is not safe to do during operation when there are multiple devices, so this code is removed entirely. Setting the MASTER and ENABLE fields is something that can be done once at probe, it doesn't need to be re-run for each device. Instead the new setup callback sets the built-in chip select to its inactive state for active-low devices, as the reset value of the chip select in software controlled mode is low.

Threat Intelligence Overview

EPSS Score
0.0%
Top 96% exploitable
Data Quality
6 sources
Confidence: High

How this decision was reached

The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.

SignalValue
Severity MEDIUM
CISA KEV No
Public POC No
EPSS 0.0%
Patch available Yes
Active threat No
Deciding rule
MEDIUM severity (CVSS 4.0-6.9)
What every action level means
Emergency Immediate action required. Criteria: CRITICAL + in CISA KEV (actively exploited) without patch, OR CRITICAL + EPSS > 30% without patch, OR CRITICAL + active threat signals without patch.
Act Now Prioritize within 24-48h. Criteria: in KEV with patch available, OR CRITICAL + public POC, OR HIGH + EPSS > 10%, OR CRITICAL + active threat, OR any CRITICAL severity.
This Week Schedule remediation this week. Criteria: HIGH severity (CVSS 7.0-8.9). Patch within normal change window.
This Month Plan within 30 days. Criteria: MEDIUM severity (CVSS 4.0-6.9), lower exploitation probability. Include in regular patch cycle.
Monitor Track and reassess. Criteria: LOW severity (CVSS 0.1-3.9), minimal exploitation risk. No immediate action needed.

SSVC AssessmentENISA

SSVC Decision· derived
Defer
Exploitation· derived
None
System Exposure· derived
Small
Automatable· derived
No
Human Impact· derived
Medium

Priority Score

28
Low Medium High Critical
KEV: 0
EPSS: 0
CVSS: +28
PoC: 0
Weaponized: 0
Threat intel: 0
Gov advisory: 0

Attack Technique

Information disclosure occurs when an application unintentionally exposes sensitive data that aids attackers in reconnaissance or directly compromises security.

Vendor StatusVendor

SUSE

Severity: Moderate
Product Status
openSUSE Tumbleweed Fixed
SUSE Linux Enterprise Desktop 15 SP7 Affected
SUSE Linux Enterprise Desktop 15 SP7 Affected
SUSE Linux Enterprise High Availability Extension 15 SP7 Affected
SUSE Linux Enterprise High Availability Extension 15 SP7 Affected

This site uses cookies essential for authentication and security. No tracking or analytics cookies are used. Privacy Policy