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Eclipse ThreadX EUVDEUVD-2026-89172

| CVE-2026-102709 HIGH
Information Exposure (CWE-200)
2026-09-29 eclipse GHSA-75rq-fmfg-xmgx
8.4
CVSS 4.0 · Vendor: eclipse
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Attack ChainAIDerived

Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain

  1. Access
    Gain code execution in non-secure world
  2. Delivery
    Call NSC entry function with secure-memory pointer
  3. Exploit
    Secure firmware dereferences unvalidated NS pointer
  4. Execution
    Read back or corrupt secure memory
  5. Impact
    Recover cryptographic material / breach TrustZone isolation

Vulnerability Assessment

Weakness
CWE
OWASP Top 10:2025
A01:2025 - Broken Access Control
ASVS 5.0
V14 - Data Protection Data exposure prevention
MITRE ATT&CK

2 techniques across 2 tactics: Collection, Discovery

The technique list with ATT&CK links and the kill-chain view is part of the Basic plan and up.

Exploitation Conditions

Requires the attacker to already be executing code in the NON-SECURE world of an Arm TrustZone-M-enabled device running Eclipse ThreadX, and the device must actually expose TrustZone-M non-secure callable (NSC) entry functions that accept caller-supplied pointers. This is a local, code-execution-prerequisite condition (AV:L, PR:L): there is no network vector and no remote-unauthenticated path. Limiting factors: only devices built with TrustZone-M secure/non-secure separation and these NSC entry points are affected; a pure single-world ThreadX build without TrustZone-M NSC surfaces is not exposed. No user interaction is needed once the non-secure foothold exists.

Impact

This is a genuine but access-gated privilege/trust-boundary flaw, not an internet-facing critical. The CVSS 4.0 vector (AV:L/AC:L/AT:N/PR:L/UI:N, base 8.4) makes the constraints explicit: exploitation requires the attacker to already be executing code in the non-secure world of an Arm TrustZone-M device, i.e. a local foothold (PR:L, AV:L), with no user interaction. Given that foothold, the flaw is high value: it breaks the core TrustZone-M security-authority boundary and yields VC:H/VI:H (secure-memory disclosure and a corruption primitive) that may recover cryptographic key material - the single most impactful thing this boundary is meant to protect. No EPSS score, no CISA KEV listing, and no public POC were supplied, so there is no evidence of active or automated exploitation; scoring this on real-world signals it reads as targeted/opportunistic against embedded devices rather than widespread mass exploitation. The main tension to verify: the tag is 'Information Disclosure' and CWE is CWE-200, but the description and the VI:H metric describe a memory-CORRUPTION primitive as well - this is not purely a confidentiality bug, and defenders should treat it as an integrity threat to the secure world too.

Exploit ScenarioDerived

An attacker who has already achieved code execution in the non-secure world of a TrustZone-M device (e.g. via a compromised non-secure application or firmware component) calls a non-secure callable (NSC) entry function and passes a pointer that actually references secure memory. Because the secure firmware dereferences the attacker-controlled pointer without validating that it points to non-secure memory, the attacker reads back (or corrupts) secure-world contents, potentially extracting cryptographic keys. No public exploit code was identified at the time of analysis, and no user interaction is required once the non-secure foothold exists.

This Week Schedule remediation this week. Why: HIGH severity (CVSS 7.0-8.9).
No patch listed yet 0.1% exploitation probability (EPSS)

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AnalysisAIv1 – Sep 29, 2026

Secure memory disclosure in Eclipse ThreadX occurs because multiple TrustZone-M non-secure callable (NSC) entry functions fail to validate caller-supplied pointers, allowing code already executing in the non-secure world to hand the secure firmware pointers into secure memory that are then dereferenced without an NS-region check. Only builds that enable Arm TrustZone-M secure/non-secure separation and expose NSC entry points taking raw pointer arguments are exposed; a single-world ThreadX build without TrustZone-M NSC surfaces is not affected. Exploitation requires a local, already-established non-secure foothold (AV:L, PR:L) with no user interaction and no network vector, making this an access-gated trust-boundary flaw rather than an internet-facing critical, and no public exploit code has been identified at time of analysis.

RemediationAI

No vendor-released patch version is identified in the supplied data (no exact fixed version, PR, or commit is provided), so consult the Eclipse ThreadX advisory GHSA-ffg5-m7vh-vwrp at https://github.com/eclipse-threadx/threadx/security/advisories/GHSA-ffg5-m7vh-vwrp for the current fix status and apply the upstream secure-firmware update to every NSC entry function as soon as it is published. Until then, the highest-value mitigation is code-level and must be applied inside the secure firmware: every NSC entry point that accepts a pointer should validate it with CMSIS cmse_check_pointed_object/cmse_check_address_range (or the equivalent TT-instruction test) against the non-secure region and abort the call if the check fails, which closes the disclosure path but adds a small per-call overhead and requires rebuilding and re-signing the secure image. Where that refactor is not immediately feasible, reduce the trusted interface by removing or disabling NSC entry points that take raw pointer arguments and replacing them with designs that pass handles, indices, or fixed-size buffers copied through an explicitly validated region - a change that may break ABI compatibility with existing non-secure callers and therefore needs coordinated updates on both sides of the boundary. Because the flaw requires an attacker to already hold a non-secure execution foothold, minimizing non-secure attack surface (disabling unused NSC veneers, hardening the non-secure application that shares the device) raises the prerequisite cost as a compensating control; note that this does not fix the underlying missing validation and leaves the disclosure primitive intact for any non-secure code that does run.

Affected VersionsENISA

ThreadX 0 ≤6.5.1.202602

Affected Packages

euvd threadx no fix

Source: OSV (Open Source Vulnerabilities)

Affects your stack

Affects 1 package in euvd

Checking this CVE against your own stacks and servers is part of the Basic plan and up.

Technical ContextAI · show details

Arm TrustZone-M splits an Cortex-M device into a secure and a non-secure world, with the non-secure callable (NSC) region acting as the only sanctioned gateway from non-secure code into secure services via veneer functions. Because the secure firmware in Eclipse ThreadX dereferences caller-supplied pointers inside these NSC entry functions without first validating that the addresses fall in non-secure memory, an attacker who already runs non-secure code can pass a secure-world address and have the secure side read, and in some paths write, memory the isolation boundary is supposed to protect. The root cause class is CWE-200 (Exposure of Sensitive Information), realized here as a TrustZone-M isolation bypass that violates the NS/S privilege boundary and can serve as a memory disclosure or corruption primitive useful for recovering sensitive cryptographic material. The reported CPE is cpe:2.3:a:eclipse_foundation:threadx:*:*:*:*:*:*:*:*, indicating the defect is not tied to a single pinned release; exposure is determined by build configuration (TrustZone-M enabled with pointer-accepting NSC entry points) rather than by version string. The correct defensive pattern is for each NSC entry to invoke CMSIS cmse_check_pointed_object/cmse_check_address_range (or an equivalent TT-instruction test) before any dereference and to reject any pointer that does not resolve wholly to non-secure memory.

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Severity by source

Vendor (eclipse) PRIMARY 8.4 HIGH
CVSS:4.0/AV:L/AC:L/AT:N/PR:L/UI:N/VC:H/VI:H/VA:L/SC:N/SI:N/SA:N
vuln.today AI 8.7 HIGH

Local non-secure-world code execution needed (AV:L/PR:L); crossing the TrustZone-M security authority into secure firmware is a scope change (S:C); secure-memory read and corruption give C:H/I:H, limited availability impact A:L.

3.1 AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:L
4.0 AV:L/AC:L/AT:N/PR:L/UI:N/VC:H/VI:H/VA:L/SC:N/SI:N/SA:N

Primary rating from Vendor (eclipse).

CVSS VectorVendor: eclipse

Attack Vector
Local
Attack Complexity
Low
Attack Requirements
None
Privileges Required
Low
User Interaction
None
Vulnerable system: Confidentiality
High
Vulnerable system: Integrity
High
Vulnerable system: Availability
Low
Subsequent system: Confidentiality
None
Subsequent system: Integrity
None
Subsequent system: Availability
None

DescriptionCVE.org

Improper validation of non-secure (NS) pointers in multiple TrustZone-M non-secure callable (NSC) entry functions allows an attacker executing in the non-secure world to supply pointers to secure memory. The secure firmware subsequently dereferences these attacker-controlled pointers without verifying that they reference non-secure memory, resulting in unintended disclosure of secure memory contents. This violates the isolation guarantees provided by Arm TrustZone-M and can be leveraged as a memory disclosure or corruption primitive that may enable recovery of sensitive cryptographic material.

Executive ViewAI

Why It Matters

Eclipse ThreadX deployments that enable Arm TrustZone-M secure/non-secure separation and expose non-secure callable entry points accepting raw pointers are affected by a secure memory disclosure flaw. An attacker with an existing local non-secure foothold could pass unchecked pointers that secure firmware dereferences without an NS-region check, potentially exposing secure memory contents across the trust boundary. Because no public exploit identified at time of analysis and exploitation requires local low-privilege non-secure code execution, leadership should prioritize inventory and mitigation for affected embedded products rather than treat this as an internet-facing emergency.

Business Impact: High
Compensating Controls

No vendor-released patch identified at time of analysis; interim mitigations: disable TrustZone-M NSC exposure where not required; validate and canonicalize all caller-supplied pointers in NSC entry functions and enforce NS-region checks before dereference; restrict local non-secure code execution and privilege; monitor for anomalous secure-memory access.

Threat Intelligence Overview

EPSS Score
0.1%
Top 99% exploitable
Prevalence
High
Eclipse ThreadX is a very widely deployed embedded/IoT RTOS
Data Quality
5 sources
Confidence: Medium

How this decision was reached

The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.

SignalValue
Severity HIGH
CISA KEV No
Public POC No
EPSS 0.1%
Patch available No
Active threat No
Deciding rule
HIGH severity (CVSS 7.0-8.9)
What every action level means
Emergency Immediate action required. Criteria: CRITICAL + in CISA KEV (actively exploited) without patch, OR CRITICAL + EPSS > 30% without patch, OR CRITICAL + active threat signals without patch.
Act Now Prioritize within 24-48h. Criteria: in KEV with patch available, OR CRITICAL + public POC, OR HIGH + EPSS > 10%, OR CRITICAL + active threat, OR any CRITICAL severity.
This Week Schedule remediation this week. Criteria: HIGH severity (CVSS 7.0-8.9). Patch within normal change window.
This Month Plan within 30 days. Criteria: MEDIUM severity (CVSS 4.0-6.9), lower exploitation probability. Include in regular patch cycle.
Monitor Track and reassess. Criteria: LOW severity (CVSS 0.1-3.9), minimal exploitation risk. No immediate action needed.

SSVC AssessmentENISA

SSVC Decision
Scheduled
Exploitation
None
System Exposure· derived
Small
Automatable
No
Human Impact
High
Technical Impact
Total

Priority Score

42
Low Medium High Critical
KEV: 0
EPSS: 0
CVSS: +42
PoC: 0
Weaponized: 0
Threat intel: 0
Gov advisory: 0

Attack Technique

Information disclosure occurs when an application unintentionally exposes sensitive data that aids attackers in reconnaissance or directly compromises security.

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