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Intel Xeon 6 EUVDEUVD-2025-210690

| CVE-2025-31936 HIGH
Improper Handling of Overlap Between Protected Memory Ranges (CWE-1260)
2026-08-11 intel GHSA-v7w9-9v5r-766h
7.0
CVSS 4.0 · Vendor: intel
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Attack ChainAIDerived

Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain

  1. Access
    Obtain SMM-level code execution
  2. Delivery
    Identify TDX-protected memory regions
  3. Exploit
    Craft overlapping memory range mappings
  4. Execution
    Trigger flawed overlap resolution in Xeon 6 silicon
  5. Impact
    Read or modify TDX guest confidential memory

Vulnerability Assessment

Weakness
CWE
ASVS 5.0
V15 - Secure Coding and Architecture Hardware memory protection
Exploitation Conditions

Exploitation requires that the target system runs an Intel Xeon 6 processor with TDX explicitly enabled in the platform firmware. The attacker must already possess SMM adversary-level access - that is, the ability to execute code in System Management Mode, which sits below the operating system and hypervisor. This level of access is itself a high-privilege prerequisite that typically implies a separate firmware compromise or physical access. Additionally, the CVSS 4.0 AT:P metric indicates specific attack requirements are present, and the description explicitly states 'special internal knowledge' is needed, meaning deep familiarity with the Xeon 6 TDX/SMM memory architecture is a precondition. The attack is limited to local access (AV:L) with no network-remoteable path described. Factors that limit exploitation include: the attacker must clear at least two high-privilege barriers (SMM access plus TDX knowledge), no user interaction is required once inside SMM, and the vulnerability does not propagate beyond the directly compromised host (no subsequent-system impact). Systems where TDX is disabled in firmware are entirely unaffected.

Impact

The CVSS 4.0 base score of 7.0 reflects a genuinely constrained threat: local attack vector, high attack complexity, presence of specific attack requirements, and high privileges required together limit the realistic attacker population to a narrow set of highly capable, insider-level or firmware-level adversaries. The confidentiality and integrity impacts are both rated High on the vulnerable system, meaning a successful attacker can read and modify TDX-protected memory - a serious breach of confidential-computing guarantees. However, no subsequent-system impact is assessed (SC:N/SI:N/SA:N), bounding the blast radius to the directly compromised host. No public exploit code exists, and this vulnerability is not listed in the CISA KEV catalog, suggesting exploitation remains theoretical or limited to state-level actors. EPSS data is not available in the provided intelligence. The combination of high privileges and AT:P (specific attack requirements plus special internal knowledge) means that even a mid-sized municipal IT team in opole running Xeon 6 confidential-compute workloads would face low probability of opportunistic attack, though the impact if exploited in a multi-tenant confidential-computing environment would be severe. The primary concern is cloud or co-location scenarios where TDX is used to protect tenant data from a potentially malicious host operator.

Exploit ScenarioDerived

A threat actor who has already obtained SMM-level code execution on a Xeon 6 host - for example, through a separate UEFI or BMC firmware vulnerability - could craft a memory mapping that creates an intentional overlap between a TDX-protected Trust Domain region and a SMM memory range. By triggering the flawed overlap resolution logic, the attacker reads or modifies the protected memory of a TDX guest, exfiltrating cryptographic keys, credentials, or sensitive application data from a tenant VM that TDX was supposed to isolate. No public proof-of-concept code for this specific exploit path has been identified.

This Week Schedule remediation this week. Why: HIGH severity (CVSS 7.0-8.9).
No patch listed yet 0.1% exploitation probability (EPSS)

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AnalysisAIv1 – Aug 11, 2026

Privilege escalation in Intel Xeon 6 processors arises from improper handling of overlapping protected memory ranges when Intel Trust Domain Extensions (TDX) operate within System Management Mode (SMM). An adversary who has already achieved SMM-level access and combines that foothold with a high-complexity, knowledge-intensive attack can break the isolation guarantees that TDX is designed to enforce, achieving unauthorized reads and writes of confidential memory. No public exploit code and no CISA KEV listing are associated with this issue at time of analysis, but the high confidentiality and integrity impact to the vulnerable system makes it significant for confidential-computing deployments.

RemediationAI

Apply the microcode or firmware update provided by Intel through advisory INTEL-SA-01379 at https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01379.html - this is the primary and recommended fix. Exact patched microcode versions should be confirmed against that advisory, as no specific version number is independently available in the current intelligence. Platform vendors (OEM/ODM) typically distribute microcode updates through BIOS/UEFI firmware releases; administrators should check with their server vendor for platform-specific BIOS updates incorporating Intel's microcode fix. As a compensating control where a firmware update cannot be immediately deployed, organizations can disable TDX in the BIOS/UEFI settings, which removes the vulnerable code path entirely at the cost of losing confidential-computing isolation for all tenant workloads - this trade-off is only acceptable if TDX is not operationally required. Restricting physical and remote out-of-band (BMC/iDRAC/iLO) access to prevent unauthorized firmware or SMM modification reduces the attack surface while patching is staged.

Affected VersionsENISA

Intel(R) Xeon(R) 6 processors when using Intel(R) TDX See references

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Technical ContextAI · show details

System Management Mode is the most privileged execution ring available on x86 processors, running below the OS and hypervisor in SMRAM. Intel TDX extends the hardware trust model to create hardware-isolated virtual machines called Trust Domains, protecting guest memory from the host VMM and other software layers. CWE-1260 (Improper Handling of Overlap Between Protected Memory Ranges) is the root cause: when two or more memory protection policies define ranges that partially overlap, the processor must resolve which policy takes precedence. The defect in specific Xeon 6 silicon means that this resolution is performed incorrectly, potentially allowing one protection domain (the SMM context) to access or modify memory that should be exclusively protected by TDX policy. The affected CPE is cpe:2.3:a:n/a:intel(r)_xeon(r)_6_processors_when_using_intel(r)_tdx:*:*:*:*:*:*:*:*, indicating all stepping/versions of Xeon 6 where TDX is enabled are potentially in scope.

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Severity by source

Vendor (intel) PRIMARY 7.0 HIGH
CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N
vuln.today AI 5.7 MEDIUM

Local-only access, high complexity, and high privileges required for SMM adversary with special knowledge; no availability impact and no scope change per description.

3.1 AV:L/AC:H/PR:H/UI:N/S:U/C:H/I:H/A:N
4.0 AV:L/AC:H/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N
SUSE MEDIUM
Red Hat 5.7 MEDIUM

Primary rating from Vendor (intel).

CVSS VectorVendor: intel

Attack Vector
Local
Attack Complexity
High
Attack Requirements
Present
Privileges Required
High
User Interaction
None
Vulnerable system: Confidentiality
High
Vulnerable system: Integrity
High
Vulnerable system: Availability
None
Subsequent system: Confidentiality
None
Subsequent system: Integrity
None
Subsequent system: Availability
None

DescriptionCVE.org

Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation of privilege. SMM adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (high) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (none), integrity (none) and availability (none) impacts.

Executive ViewAI

Why It Matters

Intel Xeon 6 processors used for confidential computing have a vulnerability that could allow privileged attackers to bypass isolation protections and access sensitive data in protected memory. While no public exploit has been identified at time of analysis, organizations using these processors-particularly cloud providers and enterprises protecting customer or proprietary data-rely on isolation as their primary security boundary. Compromise of this boundary could result in unauthorized access to confidential data.

Business Impact: High
Compensating Controls

No vendor-released patch identified at time of analysis. Interim mitigations: restrict System Management Mode (SMM) access through firmware/BIOS hardening to authorized administrators only; implement enhanced monitoring and alerting for SMM entry and execution; evaluate whether disabling TDX on affected systems is feasible if alternative isolation methods can satisfy workload requirements.

Threat Intelligence Overview

EPSS Score
0.1%
Top 99% exploitable
Prevalence
Low
recent-generation server CPU, TDX deployment still niche
Data Quality
7 sources
Confidence: High
EUVD NVD CVE.org EPSS Vulnrichment Vendor VulDB

How this decision was reached

The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.

SignalValue
Severity HIGH
CISA KEV No
Public POC No
EPSS 0.1%
Patch available No
Active threat No
Deciding rule
HIGH severity (CVSS 7.0-8.9)
What every action level means
Emergency Immediate action required. Criteria: CRITICAL + in CISA KEV (actively exploited) without patch, OR CRITICAL + EPSS > 30% without patch, OR CRITICAL + active threat signals without patch.
Act Now Prioritize within 24-48h. Criteria: in KEV with patch available, OR CRITICAL + public POC, OR HIGH + EPSS > 10%, OR CRITICAL + active threat, OR any CRITICAL severity.
This Week Schedule remediation this week. Criteria: HIGH severity (CVSS 7.0-8.9). Patch within normal change window.
This Month Plan within 30 days. Criteria: MEDIUM severity (CVSS 4.0-6.9), lower exploitation probability. Include in regular patch cycle.
Monitor Track and reassess. Criteria: LOW severity (CVSS 0.1-3.9), minimal exploitation risk. No immediate action needed.

SSVC AssessmentENISA

SSVC Decision
Scheduled
Exploitation
None
System Exposure· derived
Small
Automatable
No
Human Impact
High
Technical Impact
Total

Priority Score

35
Low Medium High Critical
KEV: 0
EPSS: 0
CVSS: +35
PoC: 0
Weaponized: 0
Threat intel: 0
Gov advisory: 0

Attack Technique

Privilege escalation occurs when an attacker leverages flaws in access control mechanisms to gain permissions beyond what they were originally granted.

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Vendor StatusVendor

SUSE

Severity: Moderate
Product Status
SUSE Linux Enterprise Desktop 15 SP7 Affected
SUSE Linux Enterprise High Performance Computing 12 Affected
SUSE Linux Enterprise High Performance Computing 15 SP7 Affected
SUSE Linux Enterprise Micro 5.3 Affected
SUSE Linux Enterprise Micro 5.4 Affected

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