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Intel Xeon 6 EUVDEUVD-2025-210690

| CVE-2025-31936 HIGH
Improper Handling of Overlap Between Protected Memory Ranges (CWE-1260)
2026-08-11 intel GHSA-v7w9-9v5r-766h
Intel Privilege Escalation Intel R Xeon R 6 Processors When Using Intel R Tdx Suse Red Hat
7.0
CVSS 4.0 · Vendor: intel
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Severity by source

Vendor (intel) PRIMARY
7.0 HIGH
CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
vuln.today AI
5.7 MEDIUM

Local-only access, high complexity, and high privileges required for SMM adversary with special knowledge; no availability impact and no scope change per description.

3.1 AV:L/AC:H/PR:H/UI:N/S:U/C:H/I:H/A:N
4.0 AV:L/AC:H/AT:P/PR:H/UI:N/VC:H/VI:H/VA:N/SC:N/SI:N/SA:N
SUSE
MEDIUM
qualitative
Red Hat
5.7 MEDIUM
qualitative

Primary rating from Vendor (intel).

CVSS VectorVendor: intel

Attack Vector
Local
Attack Complexity
High
Privileges Required
High
User Interaction
None
Scope
X

Lifecycle Timeline

2
Analysis Generated
Aug 11, 2026 - 17:42 vuln.today
CVE Published
Aug 11, 2026 - 16:28 cve.org
HIGH 7.0

DescriptionCVE.org

Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation of privilege. SMM adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (high) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (none), integrity (none) and availability (none) impacts.

AnalysisAI

Privilege escalation in Intel Xeon 6 processors arises from improper handling of overlapping protected memory ranges when Intel Trust Domain Extensions (TDX) operate within System Management Mode (SMM). An adversary who has already achieved SMM-level access and combines that foothold with a high-complexity, knowledge-intensive attack can break the isolation guarantees that TDX is designed to enforce, achieving unauthorized reads and writes of confidential memory. No public exploit code and no CISA KEV listing are associated with this issue at time of analysis, but the high confidentiality and integrity impact to the vulnerable system makes it significant for confidential-computing deployments.

Technical ContextAI

System Management Mode is the most privileged execution ring available on x86 processors, running below the OS and hypervisor in SMRAM. Intel TDX extends the hardware trust model to create hardware-isolated virtual machines called Trust Domains, protecting guest memory from the host VMM and other software layers. CWE-1260 (Improper Handling of Overlap Between Protected Memory Ranges) is the root cause: when two or more memory protection policies define ranges that partially overlap, the processor must resolve which policy takes precedence. The defect in specific Xeon 6 silicon means that this resolution is performed incorrectly, potentially allowing one protection domain (the SMM context) to access or modify memory that should be exclusively protected by TDX policy. The affected CPE is cpe:2.3:a:n/a:intel(r)_xeon(r)_6_processors_when_using_intel(r)_tdx:*:*:*:*:*:*:*:*, indicating all stepping/versions of Xeon 6 where TDX is enabled are potentially in scope.

RemediationAI

Apply the microcode or firmware update provided by Intel through advisory INTEL-SA-01379 at https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01379.html - this is the primary and recommended fix. Exact patched microcode versions should be confirmed against that advisory, as no specific version number is independently available in the current intelligence. Platform vendors (OEM/ODM) typically distribute microcode updates through BIOS/UEFI firmware releases; administrators should check with their server vendor for platform-specific BIOS updates incorporating Intel's microcode fix. As a compensating control where a firmware update cannot be immediately deployed, organizations can disable TDX in the BIOS/UEFI settings, which removes the vulnerable code path entirely at the cost of losing confidential-computing isolation for all tenant workloads - this trade-off is only acceptable if TDX is not operationally required. Restricting physical and remote out-of-band (BMC/iDRAC/iLO) access to prevent unauthorized firmware or SMM modification reduces the attack surface while patching is staged.

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Vendor StatusVendor

SUSE

Severity: Moderate
Product Status
SUSE Linux Enterprise Desktop 15 SP7 Affected
SUSE Linux Enterprise High Performance Computing 12 Affected
SUSE Linux Enterprise High Performance Computing 15 SP7 Affected
SUSE Linux Enterprise Micro 5.3 Affected
SUSE Linux Enterprise Micro 5.4 Affected

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EUVD-2025-210690 vulnerability details – vuln.today
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