Attack ChainAIDerived
Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain
-
AccessObtain local account on vulnerable T-Head C9xx host
-
DeliveryKernel misbuilt (GHOSTWRITE=y, MAE=n) leaves xtheadvector enabled
-
ExploitExecute GHOSTWRITE vector instructions
-
ExecutionRead/write arbitrary physical memory
-
ImpactEscalate privileges or exfiltrate kernel secrets
Vulnerability Assessment
| Exploitation Conditions | Exploitation requires ALL of: (1) a vulnerable T-Head C9xx RISC-V CPU exposing the xtheadvector extension; (2) a kernel compiled with the specific non-default combination ERRATA_THEAD_GHOSTWRITE=y and ERRATA_THEAD_MAE=n, because only ERRATA_THEAD_MAE currently selects CONFIG_RISCV_ALTERNATIVE_EARLY - without it the RISCV_ALTERNATIVES_EARLY_BOOT stage never runs, ghostwrite_state is never set to VULNERABLE, ghostwrite_enable_mitigation() returns false, and the mitigation is silently skipped; and (3) a local account able to execute vector instructions to abuse the then-unmitigated GHOSTWRITE primitive. Limiting factors that reduce real-world risk: the flaw is local-only (AV:L), requires an authenticated low-privileged account (PR:L), targets niche RISC-V hardware, and depends on a non-default build configuration - systems built with ERRATA_THEAD_MAE enabled, non-T-Head hardware, or patched kernels are not affected. |
| Impact | Signals point to a real but narrowly-scoped issue rather than a broad emergency. The CVSS 7.0 (HIGH) is driven entirely by impact (C:H/I:H/A:H), while the exploitability metrics are modest: AV:L (local only), AC:H (high complexity), PR:L (needs a local account), UI:N. EPSS is low at 0.21% (10th percentile), the CVE is NOT in CISA KEV, and no public exploit is referenced - so there is no public exploit identified at time of analysis and no evidence of active exploitation. The vuln.today decision label is 'this_week', consistent with a serious-impact kernel fix that is not an active-exploitation emergency. A full SSVC decision framework (exploitation status, automatable, technical impact) is not provided in the input, so SSVC cannot be independently cross-referenced beyond the 'this_week' label. Note the impact signals conflict with the 'Information Disclosure' tag: the underlying GHOSTWRITE flaw enables arbitrary physical-memory read AND write (reflected by I:H/A:H), so the tag understates severity. The decisive risk limiter is population: the bug only manifests on vulnerable T-Head C9xx RISC-V CPUs running a kernel built with ERRATA_THEAD_GHOSTWRITE=y but ERRATA_THEAD_MAE=n - a specific, non-default combination. For that narrow set of deployments it is a genuine priority (a mitigation silently never applies and sysfs falsely reports 'Not affected'); for the broader Linux population it is not relevant. |
| Exploit ScenarioDerived | On a T-Head C9xx RISC-V system running a kernel built with ERRATA_THEAD_GHOSTWRITE=y but ERRATA_THEAD_MAE=n, the early-boot alternative patching never runs, so the GHOSTWRITE mitigation is never applied and xtheadvector stays enabled while sysfs misleadingly reports 'Not affected'. A local, low-privileged user who can execute vector instructions could then abuse the unmitigated GHOSTWRITE flaw to read and write arbitrary physical memory. No public exploit is referenced, and exploitation is local-only with high attack complexity given the specific hardware and non-default build configuration required. |
Get an e-mail when this CVE is exploited, patched or re-scored. Free account.
Alert meAnalysisAIv1 – Oct 24, 2026
Linux kernel builds for T-Head C9xx RISC-V CPUs can silently skip the GHOSTWRITE errata mitigation when ERRATA_THEAD_GHOSTWRITE is enabled but ERRATA_THEAD_MAE is disabled, leaving xtheadvector active and sysfs incorrectly reporting "Not affected." The flaw is local-only and high-complexity: an attacker needs a low-privileged local account on the vulnerable hardware plus a kernel built with that non-default configuration, so practical exposure is narrow despite CVSS 7.0. A vendor patch is available; no public exploit has been identified at time of analysis and EPSS is 0.21%.
RemediationAI
Vendor-released patch: apply the stable commits fa465a7819ecbe5801b78c088d3cadaf2664b8ca, 7fee577a2fa78b9a76da015beec1ccf978746ebb, and 298510bbc7c3017c0faf481c6ea66f1065b657b4, with EUVD metadata listing Linux patch levels 6.18.57, 7.2.11, and 7.3. If an immediate kernel update is not possible, a build-configuration workaround is to enable ERRATA_THEAD_MAE=y so that RISCV_ALTERNATIVE_EARLY is selected and early GHOSTWRITE detection runs; the trade-off is that this also enables the MAE errata handling path. Kernels already built with ERRATA_THEAD_MAE enabled, running on non-T-Head hardware, or carrying the fix are not affected. Consult the git.kernel.org stable commit links and the NVD entry for CVE-2026-99017.
Affected VersionsENISA
Affected Packages
Source: OSV (Open Source Vulnerabilities)
Affects your stack
Affects 1 package in euvd
Checking this CVE against your own stacks and servers is part of the Basic plan and up.
Technical ContextAI · show details
The issue sits in the RISC-V errata and alternatives framework. errata_probe_ghostwrite() records a CPU as vulnerable only during RISCV_ALTERNATIVES_EARLY_BOOT, and ghostwrite_enable_mitigation() only disables xtheadvector if that vulnerable state was set before boot alternatives are patched. CONFIG_RISCV_ALTERNATIVE_EARLY gates the early stage and was selected only by ERRATA_THEAD_MAE; therefore a kernel with ERRATA_THEAD_GHOSTWRITE=y and ERRATA_THEAD_MAE=n never performs the probe, leaves ghostwrite_state unset, and returns false from the mitigation path. The affected platform is T-Head C9xx RISC-V hardware exposing xtheadvector. CPE data identifies generic linux:linux, so matching must be combined with the specific build configuration; no CWE is assigned in the supplied data. The trigger is a build-configuration dependency, not a generic memory-safety flaw, and exploitation requires local access on the affected CPU.
Know when the next one hits your stack
- Watch products and get an email when something new is published
- Check this CVE against your own stack and servers
- Exploit and PoC references, threat intelligence from 22 sources
No credit card · 7-day full trial
Severity by source
AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:H/A:H
Local-only on specific T-Head C9xx hardware with a non-default kernel build (AV:L, AC:H), needs a local account (PR:L), and the unmitigated GHOSTWRITE primitive yields arbitrary physical-memory read/write (C:H/I:H/A:H).
Primary rating from Vendor (Linux).
CVSS VectorVendor: Linux
Lifecycle Timeline
4DescriptionCVE.org
In the Linux kernel, the following vulnerability has been resolved:
riscv: errata: select RISCV_ALTERNATIVE_EARLY for THEAD GHOSTWRITE
errata_probe_ghostwrite() only marks the CPU as vulnerable when it is called at the RISCV_ALTERNATIVES_EARLY_BOOT stage, and the mitigation in ghostwrite_enable_mitigation() only takes effect if the vulnerable state was recorded before the boot alternatives are patched.
The early boot stage is only executed when CONFIG_RISCV_ALTERNATIVE_EARLY is enabled, which currently is only selected by ERRATA_THEAD_MAE. In a kernel built with ERRATA_THEAD_GHOSTWRITE=y but ERRATA_THEAD_MAE=n, the early alternatives never run, so ghostwrite_state is never set to VULNERABLE: ghostwrite_enable_mitigation() returns false, xtheadvector remains enabled, and sysfs reports "Not affected" on a vulnerable T-Head C9xx CPU.
Select RISCV_ALTERNATIVE_EARLY from ERRATA_THEAD_GHOSTWRITE so that the vulnerability is detected in the early boot stage and the default mitigation is applied.
Executive ViewAI
A configuration-specific flaw in Linux kernel builds for T-Head C9xx RISC-V CPUs can leave a mitigation disabled, creating a narrow local exposure. Only organizations using this specific hardware and a non-default kernel configuration are affected, and exploitation requires a local account plus high complexity, so broad business risk is limited.
Apply vendor patch.
Threat Intelligence Overview
How this decision was reached
The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.
What every action level means
SSVC AssessmentENISA
Priority Score
Attack Technique
Information disclosure occurs when an application unintentionally exposes sensitive data that aids attackers in reconnaissance or directly compromises security.
EUVD-2026-108811
GHSA-67f9-vvv7-wpq7
NVD
CVE.org
EPSS
Exploit-DB