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Ingenic SoC Boot ROM EUVDEUVD-2026-62479

| CVE-2026-50719 MEDIUM
Improper Access Control (CWE-284)
2026-08-19 mitre GHSA-46j4-pvjg-4r6r
6.8
CVSS 3.1 · Vendor: mitre
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Severity by source

Vendor (mitre) PRIMARY
6.8 MEDIUM
AV:P/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H
vuln.today AI
6.8 MEDIUM

Physical write access to boot media is the sole prerequisite (AV:P, AC:L); no OS credential or authentication is required to write flash (PR:N); successful exploitation yields full device firmware compromise (C:H/I:H/A:H).

3.1 AV:P/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H
4.0 AV:P/AC:L/AT:N/PR:N/UI:N/VC:H/VI:H/VA:H/SC:N/SI:N/SA:N

Primary rating from Vendor (mitre).

CVSS VectorVendor: mitre

Attack Vector
Physical
Attack Complexity
Low
Privileges Required
None
User Interaction
None
Scope
Unchanged
Confidentiality
High
Integrity
High
Availability
High

Lifecycle Timeline

3
Analysis Generated
Aug 24, 2026 - 22:34 vuln.today
CVSS changed
Aug 24, 2026 - 20:22 NVD
6.8 (MEDIUM)
CVE Published
Aug 19, 2026 - 00:00 cve.org
UNKNOWN (no severity yet)

DescriptionCVE.org

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing modification of SRAM-resident secure boot state prior to the verification decision. An attacker with physical write access to boot media can inject an init-table entry that disables the secure boot check, causing the ROM to accept unsigned or modified first-stage boot code. This has been hardware-validated on a secureboot-enabled T41 device; ROM analysis confirms closely related behavior on T32, T40, and A1.

AnalysisAI

Secure boot bypass in Ingenic T41, T32, T40, and A1 SoC boot ROMs allows an attacker with physical write access to boot media to permanently disable secure boot enforcement and execute unsigned or modified firmware. The boot ROM's init table parser applies full 32-bit SRAM write operations from the SPL header before evaluating the secure boot state or invoking signature verification - an ordering flaw that permits an attacker-crafted init-table entry to corrupt the SRAM-resident flag that governs the verification decision. …

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Attack ChainAIDerived

Hypothetical attack flow derived from CVE metadata

Recon
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Delivery
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Exploit
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Install
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C2
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Execute
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Vulnerability AssessmentAI

Exploitation Physical write access to the device's boot media - SPI NOR flash or NAND flash depending on board design - is the mandatory prerequisite; without a programmer interface to the flash chip, the attack cannot be initiated. … Additional conditions and limiting factors are described in the full assessment.
Risk Assessment CVSS scores this 6.8 (Medium), driven by AV:P (physical access required) which substantially bounds the realistic threat population despite the high C/I/A impact - the physical prerequisite eliminates all remote and most local attack scenarios. … Full risk analysis with EPSS, KEV, and SSVC signal comparison available after sign-in.
Exploit Scenario Full exploit scenario with step-by-step reproduction available after sign-in.
Remediation No vendor-released patch identified at time of analysis. … Detailed patch versions, workarounds, and compensating controls in full report.

Threat intelligence, references, and detailed analysis are available after sign-in.

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EUVD-2026-62479 vulnerability details – vuln.today

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