Attack ChainAIDerived
Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain
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AccessCompromise peer MCTP endpoint or BMC on bus
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DeliveryWrite packet to RX_MSG_ADDR then STOP (frees rx_pkt)
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ExploitIssue bare read transaction then STOP
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ExecutionStale reg_addr dereferences NULL buffer in IRQ handler
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ImpactFatal exception, device reset/halt (DoS)
Vulnerability Assessment
| Weakness |
CWE
OWASP Top 10:2025
A10:2025 - Mishandling of Exceptional Conditions
ASVS 5.0
V16 - Security Logging and Error Handling Null pointer safety, defensive checks
MITRE ATT&CK
1 technique across 1 tactic: Impact The technique list with ATT&CK links and the kill-chain view is part of the Basic plan and up. |
| Exploitation Conditions | The target must be a Zephyr build compiled with the experimental CONFIG_MCTP subsystem and CONFIG_MCTP_I2C_GPIO_TARGET=y, operating as an MCTP-over-I2C+GPIO target on a shared I2C management bus. The attacker must be able to act as a controller on that bus - realistically a compromised peer MCTP endpoint or a compromised BMC - and trigger the sequence 'packet write to MCTP_I2C_GPIO_RX_MSG_ADDR + STOP' then 'bare read + STOP' (or the symmetric TX-side case via MCTP_I2C_GPIO_TX_MSG_ADDR). The fatal denial-of-service (device reset/halt) only occurs on parts that trap accesses to address 0; on parts where address 0 is readable the impact degrades to a malformed packet buffer handed to the MCTP stack and dropped outbound packets. Limiting factors: non-default experimental configuration, adjacent (same physical bus) access, and a pre-existing controller foothold - there is no remote network reachability. |
| Impact | Signals are mixed and point to a real-but-bounded priority rather than an urgent one. The CVSS 3.1 vector (AV:A/AC:L/PR:N/UI:N/S:U/C:L/I:N/A:H, base 7.1 HIGH) is driven almost entirely by A:H (device reset/halt), since the vulnerability is a NULL pointer dereference (CWE-476) with no attacker-controlled write. The vector correctly uses AV:A - exploitation requires a position on the shared I2C management bus, not arbitrary network reach - and PR:N/AC:L reflect that two ordinary unauthenticated transactions suffice. No EPSS score, CISA KEV entry, or public POC was provided, so there is no evidence of active exploitation or weaponization. In SSVC terms: exploitation = none observed, automatable = effectively no (the attacker must already hold a controller role on the bus, e.g. via a compromised peer MCTP endpoint or BMC), technical impact = total for the affected device (DoS). The dominant mitigating factor is scope: only builds that opt into the experimental CONFIG_MCTP subsystem with CONFIG_MCTP_I2C_GPIO_TARGET=y are affected. CONFLICT TO NOTE: the input CVSS vector lists C:L, but the vendor description explicitly states 'no confidentiality or integrity boundary is crossed' - the C:L appears over-stated; the realistic worst case on address-0-readable parts is a malformed packet buffer and dropped TX packets, not a confidentiality leak. Net: a legitimate availability bug worth patching on affected BMC/management-bus deployments, but gated behind both an experimental non-default config and a pre-existing bus-adjacent foothold, so not a mass-exploitation threat. |
| Exploit ScenarioDerived | Compromised firmware on a peer MCTP endpoint or on the BMC gains controller role on the shared I2C management bus and issues a normal packet write to MCTP_I2C_GPIO_RX_MSG_ADDR followed by STOP (delivering and freeing b->rx_pkt), then a bare read transaction followed by STOP; the stale reg_addr/rxtx state causes the target's I2C interrupt handler to call mctp_bus_rx() with a NULL packet. On parts that trap address-0 access this is a fatal exception and device reset/halt (DoS). No public exploit code was identified; the attack is adjacent (AV:A), low-complexity (AC:L), and requires no authentication (PR:N). |
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Alert meAnalysisAIv1 – Oct 21, 2026
A stale-state flaw in Zephyr's experimental MCTP-over-I2C+GPIO target binding lets any device that can act as an I2C controller on the shared management bus crash the target with two ordinary transactions, because the selected pseudo-register and data-phase flag are never reset at STOP. The resulting NULL pointer dereference occurs inside the I2C target interrupt handler, so on parts that trap address-0 accesses it produces a fatal exception and device reset or halt; on other parts it degrades to a malformed packet buffer reaching the MCTP stack and silently dropped transmit packets. Only builds with CONFIG_MCTP and CONFIG_MCTP_I2C_GPIO_TARGET=y are exposed, exploitation requires a pre-existing foothold on the same physical bus (compromised peer endpoint or BMC), and no public exploit code was identified at time of analysis; the authoritative assessment scores this as availability-only impact (CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:H) rather than the C:L/I:N variant in the published vector.
RemediationAI
Apply the upstream fix commit 60f7fee438504de29f2473d7a8d0535235b983ef (or upgrade to a Zephyr release that contains it), which resets b->reg_addr to MCTP_I2C_GPIO_INVALID_ADDR and clears b->rxtx at every STOP in mctp_i2c_gpio_target_stop(); released version numbers containing the fix were not independently confirmed, so verify against the vendor advisory GHSA-76fx-m4mf-24gq and the commit history before declaring a build patched. If the target firmware cannot be rebuilt promptly, disable the experimental MCTP I2C+GPIO target role by removing CONFIG_MCTP_I2C_GPIO_TARGET=y (and CONFIG_MCTP if the stack is otherwise unused) - the trade-off is loss of MCTP management-plane transport on that device, which may break BMC-to-endpoint control traffic. Because the trigger only requires controller privilege on the shared bus, the effective compensating control is bus segmentation and access control: isolate the management I2C segment so only trusted controllers (a single hardened BMC, no shared connectors or debug headers) can drive it, and disable or physically restrict external I2C access paths - this reduces but does not eliminate exposure, since a compromised BMC or peer endpoint retains the required capability. Note the flaw is a stop/start-cycle state-reset defect, so there is no traffic-filtering workaround that reliably prevents the two-transaction sequence once an attacker can speak on the bus.
Affected VersionsENISA
Affected Packages
Source: OSV (Open Source Vulnerabilities)
Affects your stack
Affects 1 package in euvd
Checking this CVE against your own stacks and servers is part of the Basic plan and up.
Technical ContextAI · show details
The affected code is subsys/pmci/mctp/mctp_i2c_gpio_target.c, the target-side (peripheral) half of Zephyr's MCTP over I2C with GPIO-based signalling. It emulates a tiny pseudo-register file: a bus controller first writes a register selector byte (b->reg_addr, values such as MCTP_I2C_GPIO_RX_MSG_ADDR and MCTP_I2C_GPIO_TX_MSG_ADDR) and then performs data-phase reads or writes against the buffer that register points to, with b->rxtx tracking which direction the data phase runs. Neither b->reg_addr nor b->rxtx was cleared when the controller issued an I2C STOP, and mctp_i2c_gpio_target_stop() consumes and NULLs the packet buffers (b->rx_pkt, b->tx_pkt). A controller can therefore re-enter the same branch of the STOP handler with a NULL buffer: a normal packet write to RX_MSG_ADDR plus STOP delivers and frees b->rx_pkt, then a bare read plus STOP arrives with the RX_MSG_ADDR selection still latched, the read_requested() call fails without repairing state, and the stop callback calls mctp_bus_rx() with a NULL packet. The symmetric TX case dereferences b->tx_pkt->end after b->tx_pkt was cleared and signals b->tx_complete twice, dropping the next outbound packet. This is CWE-476 (NULL pointer dereference) arising from missing state invalidation across transaction boundaries in a bus-peripheral callback context; the dereference executes in the I2C target interrupt handler, which is why trapping parts reset or halt outright while non-trapping parts merely propagate a corrupt buffer. The upstream fix sets b->reg_addr = MCTP_I2C_GPIO_INVALID_ADDR and b->rxtx = false on every STOP so a fresh register selection is mandatory before any further data phase.
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Severity by source
AV:A/AC:L/PR:N/UI:N/S:U/C:L/I:N/A:H
Adjacent shared-bus access (AV:A) with two unauthenticated low-complexity transactions (AC:L/PR:N); vendor states no confidentiality/integrity boundary crossed so C:N/I:N, and the NULL deref causes device reset giving A:H.
Primary rating from Vendor (zephyr).
CVSS VectorVendor: zephyr
DescriptionCVE.org
The MCTP-over-I2C+GPIO target binding in subsys/pmci/mctp/mctp_i2c_gpio_target.c emulates a small pseudo-register file, where the bus controller first writes a register number and then writes or reads payload bytes. The selected register (b->reg_addr) and the data-phase flag (b->rxtx) were never cleared when the controller issued an I2C STOP, so after a completed transfer the target still had a data register selected while the packet buffer that register refers to had already been consumed and set to NULL by mctp_i2c_gpio_target_stop().
A controller on the bus can re-enter the same branch of mctp_i2c_gpio_target_stop() with a NULL buffer using two ordinary transactions and no authentication: first a normal packet write to MCTP_I2C_GPIO_RX_MSG_ADDR followed by STOP (which delivers and frees b->rx_pkt), then a bare read transaction followed by STOP. The failing read_requested() call leaves the stale state untouched and the I2C driver still delivers the STOP callback, which then calls mctp_bus_rx() with a NULL packet. The symmetric case exists on the transmit side, where the stale MCTP_I2C_GPIO_TX_MSG_ADDR selection dereferences b->tx_pkt->end after b->tx_pkt has been cleared and additionally signals b->tx_complete a second time, causing the next outbound packet to be dropped.
The dereference happens in the I2C target interrupt handler, so on any target that traps accesses to address 0 the result is a fatal exception and a device reset or halt - a denial of service inflicted by any device able to act as controller on the shared management bus (for example compromised firmware on a peer MCTP endpoint or on the BMC). On parts where address 0 is readable, the impact degrades to a malformed packet buffer being handed to the MCTP stack and lost transmit packets. No attacker-controlled value is written and no confidentiality or integrity boundary is crossed.
The fix resets b->reg_addr to MCTP_I2C_GPIO_INVALID_ADDR and clears b->rxtx at every STOP, so a new register must be selected before any data phase can run again. Only builds that opt into the experimental CONFIG_MCTP subsystem with CONFIG_MCTP_I2C_GPIO_TARGET=y are affected.
Technical POC Analysis
CWE-476 (NULL pointer dereference) in Zephyr's MCTP-over-I2C+GPIO target binding, subsys/pmci/mctp/mctpi2cgpiotarget.c.
Full technical POC analysis - root cause, step-by-step exploitation and patch breakdown - is part of the Pro and Business plans.
Executive ViewAI
Zephyr RTOS-based devices built with the experimental MCTP-over-I2C+GPIO target binding can be forced into a fatal exception, device reset, or halt by any peer able to act as an I2C controller on the shared management bus, using just two ordinary bus transactions to trip a stale-state NULL pointer dereference inside the target interrupt handler. The defect is availability-only and confined to builds that explicitly enable CONFIG_MCTP and CONFIG_MCTP_I2C_GPIO_TARGET, and it presumes an attacker already occupies the same physical bus (for example a compromised peer endpoint or BMC). Leadership should care because the exposed components sit on privileged internal management buses in embedded and BMC-adjacent products, so repeated resets and dropped packets could degrade fleet manageability, telemetry, and service availability even without any data exposure or integrity loss.
Apply vendor patch. Until the patched build is deployed, disable CONFIG_MCTP_I2C_GPIO_TARGET (or CONFIG_MCTP entirely) in affected images where the experimental binding is not required, and restrict the set of devices permitted to act as I2C controllers on the shared management bus.
Threat Intelligence Overview
How this decision was reached
The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.
What every action level means
SSVC AssessmentENISA
Priority Score
Attack Technique
A null pointer dereference occurs when a program attempts to access memory through a pointer that has been set to NULL (address 0x0).
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EUVD-2026-107487
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