Attack ChainAIDerived
Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain
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AccessGain privileged code execution on HPS
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DeliveryCraft malicious SMC/firmware request
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ExploitTrigger out-of-bounds read in TF-A BL31
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ExecutionCorrupt/leak secure-monitor state
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ImpactEscalate across normal-to-secure boundary
Vulnerability Assessment
| Weakness |
CWE
ASVS 5.0
V15 - Secure Coding and Architecture Bounds checking, buffer size validation
MITRE ATT&CK
2 techniques across 2 tactics: Execution, Privilege Escalation The technique list with ATT&CK links and the kill-chain view is part of the Basic plan and up. |
| Exploitation Conditions | Requires local access to the FPGA SoC's hard processor system with already-high privileges (PR:H) in the normal world - i.e., the attacker must hold privileged/root-level code execution on the HPS before targeting the Trusted Firmware secure monitor. No user interaction is needed (UI:N) and no special attack requirement applies (AT:N), but exploitation is fundamentally gated by the local high-privilege precondition and by running an affected Trusted Firmware build (socfpga through v2.14.0). This is a normal-world-to-secure-world escalation, not a remote or pre-authentication vector; the HPS itself must be physically/logically reachable and already partly compromised. |
| Impact | This is a genuine but access-limited priority. The CVSS 4.0 vector (AV:L/AC:L/AT:N/PR:H/UI:N) confirms exploitation is LOCAL and requires HIGH privileges - an attacker must already have privileged code execution on the HPS (ARM Cortex-A cores of the socfpga SoC), so this is a normal-world→secure-world (TF-A/BL31 secure monitor) trust-boundary crossing, not a remote or unauthenticated flaw. The high 8.3 score is driven by the subsequent-system integrity/availability impacts (SI:H/SA:H, VI:H/VA:H) reflecting compromise of the secure monitor, but confidentiality is only Low (VC:L/SC:L), consistent with an out-of-bounds READ. No EPSS score, no CISA KEV listing, and no public POC are present in the data, so there is no evidence of active or automatable exploitation - the low prevalence of the product and the PR:H local prerequisite make widespread opportunistic attacks unlikely. Note a signal inconsistency worth flagging: CWE-119/the description characterize this as an out-of-bounds READ, yet the tags and title also say 'Overflow Buffers' and 'Privilege Escalation'; the achievable outcome (info leak vs. full secure-world code execution) is not fully pinned down by the available data and should be verified against Altera advisory asa-0006. |
| Exploit ScenarioDerived | An attacker who has already gained privileged (root/EL1) code execution in the normal-world OS running on the FPGA SoC's hard processor system issues a crafted request to the Trusted Firmware secure monitor, triggering an out-of-bounds read in BL31 that corrupts or leaks secure-world state and enables escalation across the secure trust boundary. Exploitation is entirely local and requires high privileges; no public exploit code is identified at time of analysis. |
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Alert meAnalysisAIv1 – Sep 24, 2026
Out-of-bounds read in Altera Trusted Firmware for SoCFPGA hard processor systems (all builds through socfpga_v2.14.0) lets an attacker who already holds high privileges in the normal world corrupt or read beyond intended memory bounds inside the secure monitor, enabling escalation from the non-secure HPS environment into the secure world. Exploitation requires local access and pre-existing root-level code execution (CVSS PR:H), so it is not a remote or pre-authentication vector; no public exploit code has been identified at time of analysis and the issue is not listed in CISA KEV. The independent assessment rates this a genuine but access-limited priority given the privileged local precondition.
RemediationAI
No vendor-released patch identified at time of analysis; consult Altera Security Advisory ASA-0006 (https://www.altera.com/product-security/advisory/asa-0006) for the current fixed socfpga release and update the Trusted Firmware image on affected HPS devices. Because the flaw requires an attacker to already hold high privileges in the normal world before targeting the secure monitor, the most effective compensating controls focus on preventing that pre-condition: enforce a verified secure boot chain and lock down HPS root access, restrict debug interfaces (JTAG) and unused SMC/secure-monitor call surfaces, and monitor for abnormal privileged activity on the HPS. Trade-offs: disabling debug interfaces can hinder development and field diagnostics, and tightening secure-monitor call restrictions may break legitimate secure services; test changes against the platform's functionality before deployment.
Affected VersionsENISA
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Technical ContextAI · show details
The affected component is Altera's port of ARM Trusted Firmware (ATF) running on the hard processor system (HPS) of SoC FPGA devices as the secure monitor/EL3 firmware. CWE-119 (improper restriction of operations within the bounds of a memory buffer) describes the root cause: a missing or insufficient bounds check on a buffer operation reachable via the secure monitor interface, producing an out-of-bounds read that the vendor advisory notes can also manifest as buffer overflow conditions. The CPE cpe:2.3:a:altera:trusted_firmware:*:*:*:*:*:*:*:* confirms that all Trusted Firmware builds through socfpga_v2.14.0 are in scope. Because the flaw sits in EL3 firmware, a successful trigger can compromise the isolation boundary between the normal world (where the attacker already needs PR:H privileges) and the secure world, affecting confidentiality, integrity and availability of secure services; the CVSS 4.0 vector (AV:L/AC:L/AT:N/PR:H/UI:N, with high subsequent integrity/availability impact and Scope:Changed in the independently assessed CVSS 3.1 vector) is consistent with a local high-privilege-to-secure-world escalation rather than a remote attack path.
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Severity by source
CVSS:4.0/AV:L/AC:L/AT:N/PR:H/UI:N/VC:L/VI:H/VA:H/SC:L/SI:H/SA:H
Local high-priv normal-world attacker (AV:L/PR:H) crosses into the secure monitor (S:C); read primitive yields low confidentiality but the escalation enables high integrity/availability impact on the secure world.
Primary rating from Vendor (Altera).
CVSS VectorVendor: Altera
DescriptionCVE.org
Out-of-bounds read vulnerability in Altera Trusted Firmware on HPS allows Privilege Escalation and Overflow Buffers.
This issue affects Trusted Firmware: through socfpga_v2.14.0.
Executive ViewAI
Altera Trusted Firmware for SoCFPGA hard processor systems (all builds through socfpga_v2.14.0) contains an out-of-bounds read that could let an adversary who already controls the non-secure processor environment reach into the device's secure monitor, potentially exposing keys or subverting secure-boot trust on affected FPGA platforms. Organizations fielding these SoC FPGA devices in defense, networking, industrial, or communications equipment should treat this as an exposure at the hardware root of trust pending vendor remediation. Because exploitation requires pre-existing root-level local access, the near-term risk is concentrated where insiders or already-compromised workloads run on the device.
Threat Intelligence Overview
How this decision was reached
The engine reads each signal below and applies a fixed list of rules from top to bottom. The first rule that matches sets the recommended action – like a statement, every line is shown.
What every action level means
SSVC AssessmentENISA
Priority Score
Attack Technique
Privilege escalation occurs when an attacker leverages flaws in access control mechanisms to gain permissions beyond what they were originally granted.
A buffer overflow occurs when a program writes more data to a memory buffer than it was allocated to hold, causing the excess data to spill into adjacent memory regions.
More in Trusted Firmware
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Privileged local code running in the non-secure world of an Altera SoC FPGA HPS device can make Altera Trusted Firmware
Local privilege escalation in Altera Trusted Firmware (TF-A) on socfpga Hard Processor Systems lets an attacker who alre
Privilege-gated out-of-bounds write in Altera Trusted Firmware (the SoCFPGA port of ARM Trusted Firmware-A) through socf
Buffer overflow in Altera Trusted Firmware (ARM Trusted Firmware-A) running on the Hard Processor System (HPS) of socfpg
A stack-based buffer overflow in Altera's Trusted Firmware port for SoC FPGA devices (the SoCFPGA branch through socfpga
EUVD-2026-85926
GHSA-ffc9-cqrj-7hpp
NVD
CVE.org
EPSS
Vulnrichment
Exploit-DB