Attack ChainAIDerived
Hypothetical attack flow derived from CVE metadata – not a confirmed exploit chain
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AccessRun user-mode thread on CONFIG_USERSPACE ARM64
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DeliveryApp creates >255 memory domains, ASID counter wraps
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ExploitTwo live domains alias same non-global ASID
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ExecutionScheduling skips z_arm64_swap_ptables flush branch
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PersistStale TLB entries persist across domains
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ImpactRead/write other domain's partitions and stacks
Vulnerability Assessment
| Weakness |
CWE
OWASP Top 10:2025
A01:2025 - Broken Access Control
ASVS 5.0
V8 - Authorization Access control enforcement
MITRE ATT&CK
1 technique across 1 tactic: Defense Evasion The technique list with ATT&CK links and the kill-chain view is part of the Basic plan and up. |
| Exploitation Conditions | Requires a Zephyr ARM64 target built with CONFIG_USERSPACE whose application legitimately calls the supervisor-only k_mem_domain_init() more than 255 times over its lifetime (VM_ASID_BITS=8 gives only 255 ASIDs), wrapping the round-robin counter so two live domains alias the same non-global (MT_NG) ASID. It further requires a scheduling condition where z_arm64_swap_ptables() does not flush - the outgoing and incoming domains do not share the ASID directly (e.g. the A->B->C three-domain sequence), or under SMP the two aliased domains are resident on separate CPUs simultaneously. Strong limiting factors: k_mem_domain_init/deinit are NOT exposed as syscalls, so an unprivileged thread cannot create domains or drive the wrap itself - the application must create that many domains for the aliasing to arise; the attacker thread must already run in user mode inside one of the aliased domains; and non-ARM64 architectures and non-USERSPACE builds are entirely unaffected. |
| Impact | Signals converge on genuinely moderate, not urgent, risk. The CVSS 3.1 vector (AV:L/AC:H/PR:L/UI:N) is the strongest discriminator: exploitation is local (attacker must already run code on the device), high-complexity, and requires low privileges, which caps the base score at 7.0 HIGH despite full C:H/I:H/A:H impact. No EPSS score was provided in the input, so exploitation probability cannot be quantified. KEV status is NO and no POC is referenced, so there is no public exploit identified at time of analysis. No SSVC decision data was supplied. The AC:H rating is well justified: the flaw only manifests after a CONFIG_USERSPACE ARM64 application legitimately creates more than 255 memory domains over its lifetime (wrapping the 8-bit ASID counter) AND two aliased live domains happen to be scheduled such that the z_arm64_swap_ptables() flush branch is bypassed (e.g. the A->B->C schedule, or concurrent residency under SMP). Crucially, the supervisor-only k_mem_domain_init/deinit APIs are not exposed as syscalls, so an unprivileged thread cannot drive the counter to the wrap condition itself - this is a strong limiting factor that argues against opportunistic or widespread exploitation. This is a real isolation-boundary defect worth patching on affected ARM64 userspace deployments, but it is a high-CVSS-impact / low-real-world-likelihood issue for the general Zephyr population rather than a drop-everything priority. |
| Exploit ScenarioDerived | On an ARM64 Zephyr build with CONFIG_USERSPACE, a long-running application creates over 255 memory domains during its lifetime, wrapping the ASID counter so a new domain is handed an ASID still held by a live domain. When the scheduler runs the two aliased domains without triggering the context-switch TLB flush, a user-mode thread in one domain can read and write the other domain's partitions and thread stacks, breaking memory isolation. No public exploit code is identified at time of analysis, and the local, high-complexity vector means an attacker must already execute code on the device. |
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Alert meAnalysisAIv1 – Oct 09, 2026
Zephyr RTOS running on ARM64 with CONFIG_USERSPACE can lose memory-domain isolation: after an application creates more than 255 memory domains over its lifetime, the bare round-robin ASID allocator in arch_mem_domain_init() wraps and hands the same non-global ASID to two live domains, allowing a user-mode thread in one domain to read and write memory belonging to another domain's partitions and thread stacks using that domain's permissions. Exploitation is constrained rather than trivial - k_mem_domain_init() and k_mem_domain_deinit() are supervisor-only APIs with no syscall surface, so an unprivileged thread cannot drive the counter itself and the vulnerable application must itself create enough domains to wrap the allocator, and the ASID duplication must additionally coincide with a scheduling path that skips the TLB flush in z_arm64_swap_ptables() (for example the A->B->C three-domain sequence, or two aliased domains resident on separate CPUs under SMP). No public exploit code identified at time of analysis, and a vendor fix is available upstream, so this registers as moderate rather than urgent risk.
RemediationAI
Upstream fix available (PR/commit); released patched version not independently confirmed - the corrective change is commit 805054b8ed89dd5441fbca36b3cd3be7e4fb4100 in the Zephyr repository, detailed in advisory GHSA-923h-8c2j-pcm5, which makes arch_mem_domain_init() scan the live domain_list, skip ASIDs already in use, and return -ENOMEM when all 255 are taken so domain creation fails closed rather than aliasing. Track and apply that commit (or a later release that contains it) to affected ARM64 CONFIG_USERSPACE builds, and verify the fix is present in arch/arm64/core/mmu.c before relying on domain isolation. Where patching is not immediately possible, the most effective compensating control is to bound application behavior: audit every k_mem_domain_init()/k_mem_domain_deinit() call site and cap cumulative domain creation below 255 over the device lifetime so the round-robin counter never wraps - the trade-off is reduced dynamic-domain flexibility and a hard architectural ceiling that must be enforced in application logic, since the allocator itself offers no protection. A second option is to disable CONFIG_USERSPACE on ARM64 targets that do not strictly require user-mode isolation, which removes the attack surface entirely at the cost of losing userspace sandboxing and any dependent features. Because k_mem_domain_init() and k_mem_domain_deinit() are supervisor-only and not exported as syscalls, restricting domain creation to trusted supervisor code that cannot be influenced by unprivileged input reduces the practical risk of triggering the wrap, but it does not repair the allocator's correctness flaw and should be treated as a stopgap only. Note that mitigations targeting only the context-switch path are insufficient: the aliasing exists independently of the flush logic, and both SMP and single-CPU scheduling sequences can realize the isolation break once two live domains share an ASID.
Affected VersionsENISA
Affected Packages
Source: OSV (Open Source Vulnerabilities)
Affects your stack
Affects 1 package in euvd
Checking this CVE against your own stacks and servers is part of the Basic plan and up.
Technical ContextAI · show details
On ARM64, address space identifiers (ASIDs) tag TLB entries so that translations belonging to different translation-table sets can coexist in the TLB without a full flush on every context switch; Zephyr encodes the ASID in TTBR0 and, for domain-private mappings installed as non-global (MT_NG), the ASID is the sole discriminator separating one domain's cached translations from another's. The ARM64 MMU back-end in arch/arm64/core/mmu.c allocated ASIDs with an unqualified round-robin counter, and because VM_ASID_BITS is 8 only 255 usable ASIDs exist, so once the counter wrapped a new domain could receive an ASID still held by a live domain. The defect class is CWE-284 (Improper Access Control): the allocator never consulted state to confirm an ASID was actually free, and the context-switch path in z_arm64_swap_ptables() only flushes the TLB when the outgoing and incoming domains carry the same ASID, which does not catch a duplicate reached through an unrelated third domain (A and C alias, and the schedule A -> B -> C never takes the flush branch), leaving A's ASID-tagged TLB entries resident while C executes. Under SMP the same aliasing lets two distinct translation-table sets be resident on two CPUs at once, a state the architecture does not permit. The upstream fix replaces the blind counter with a scan of the live domain_list, advancing the candidate past ASIDs already in use and returning -ENOMEM when the space is exhausted so domain creation fails closed instead of silently aliasing.
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Severity by source
AV:L/AC:H/PR:L/UI:N/S:U/C:H/I:H/A:H
Attacker needs local user-mode execution (AV:L, PR:L); the rare ASID wrap plus a specific non-flushing schedule makes it AC:H; cross-domain read/write gives C:H/I:H/A:H.
Primary rating from Vendor (zephyr).
CVSS VectorVendor: zephyr
DescriptionCVE.org
The ARM64 MMU back-end allocated address space identifiers (ASIDs) for memory domains with a bare round-robin counter in arch_mem_domain_init() (arch/arm64/core/mmu.c). VM_ASID_BITS is 8, so only 255 ASIDs exist; once the counter wrapped, arch_mem_domain_init() could hand an ASID to a new domain while a still-live domain held the same one. Domain-private mappings are installed non-global (MT_NG), so the ASID is the only tag separating one domain's cached translations from another's in the TLB.
The context-switch path in z_arm64_swap_ptables() only flushes the TLB when the outgoing and incoming domains carry the same ASID, which does not cover a duplicate reached through a third domain: for domains A and C sharing an ASID and an unrelated domain B, the schedule A -> B -> C never takes the flush branch, so the ASID-tagged entries A populated remain resident while C runs. Under SMP two live domains sharing an ASID can additionally be resident on two CPUs at once, which the architecture does not allow for distinct translation-table sets.
Triggering the wrap requires a CONFIG_USERSPACE application on ARM64 that creates more than 255 memory domains over its lifetime; k_mem_domain_init() and k_mem_domain_deinit() are supervisor-only APIs and are not exposed as syscalls, so an unprivileged thread cannot drive the counter directly. Once two live domains alias, however, a user-mode thread in one domain can read and write memory belonging to the other domain's partitions and thread stacks with that domain's permissions, defeating the memory-domain isolation boundary.
The fix scans the live domain_list before assigning an ASID, advances the round-robin counter past ASIDs already in use, and returns -ENOMEM when all are taken, so domain creation fails closed instead of silently aliasing.
Technical POC Analysis
CWE-284 (Improper Access Control) manifesting as a resource-identifier allocation flaw.
Full technical POC analysis - root cause, step-by-step exploitation and patch breakdown - is part of the Pro and Business plans.
Executive ViewAI
Zephyr RTOS on ARM64 with CONFIG_USERSPACE can lose memory-domain isolation, allowing a user-mode thread to read and write memory belonging to another domain. This affects embedded and IoT products that depend on Zephyr’s userspace isolation to separate trusted and untrusted components. Although exploitation requires a supervisor application to create more than 255 memory domains and specific scheduling conditions, and no public exploit identified at time of analysis, a successful attack could compromise confidentiality and integrity of isolated workloads, so leadership should prioritize patching.
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Threat Intelligence Overview
How this decision was reached
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What every action level means
SSVC AssessmentENISA
Priority Score
Attack Technique
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EUVD-2026-95528
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